Senior RTL-to-GDS Design & Verification Engineer

Synopsys, Inc.; Malaysia; Hybrid; MYR 150,000 - 230,000; Full time

Benefits offered by this job

Health benefits

Financial benefits

Job summary

Synopsys, Inc. in Malaysia seeks a Senior Applications Engineer with RTL2GDS expertise to support functional verification and physical design implementation using Formaty and Fusion Compiler.

You will debug complex closure issues at advanced nodes and deliver ECOs on tight tapeout schedules while building automation in Python, Perl, and TCL. The role involves collaborating with R&D and engaging with customers, including senior engineers and design leads, to provide practical design solutions and

Qualifications

• Bachelor's degree in Electrical or Computer Engineering with 5–8 years ASIC or CAD engineering experience.
• Direct experience in functional verification and place-and-route across RTL2GDS flow.
• Proficiency in Python, Perl and TCL for automation and workflows.

Responsibilities

• Support functional verification and physical design implementation using Synopsys tools (Formality, Fusion Compiler).
• Debug timing, power, and area closure issues at 5nm and below.
• Deliver ECO solutions that meet tapeout schedules without compromising design integrity.
• Develop automation scripts in Python, Perl, and TCL to streamline workflows.
• Collaborate with R&D to reproduce issues and feed real-world use cases into product development.
• Present solutions to senior engineers and design leads during critical phases.
• Work across RTL2GDS flow from front-end verification to back-end signoff.

Skills

ASIC engineering

CAD tools

Scripting (Python)

Scripting (Perl)

Scripting (TCL)

English proficiency

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Formality

Formality-ECO

Fusion Compiler

Job description

Synopsys, Inc. in Malaysia seeks a Senior Applications Engineer with RTL2GDS expertise to support functional verification and physical design implementation using Formaty and Fusion Compiler.

You will debug complex closure issues at advanced nodes and deliver ECOs on tight tapeout schedules while building automation in Python, Perl, and TCL. The role involves collaborating with R&D and engaging with customers, including senior engineers and design leads, to provide practical design solutions and