Pre-Silicon FPGA Validation & Image Build Engineer

UST; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST seeks an FPGA Validation & Image Build Engineer to support FPGA-based pre-silicon validation activities. The role focuses on FPGA image generation, IP validation, regression execution, and build automation, collaborating with RTL, verification, firmware, and platform teams to ensure FPGA prototypes and IP work before silicon.

The engineer will automate build and validation workflows, analyze failures, and maintain validation docs and logs, contributing to CI/CD environments and defect

Qualifications

• Experience in FPGA validation, prototyping, or pre-silicon validation.
• Hands-on experience with FPGA image generation/build flows.
• Good understanding of digital design concepts and SoC/IP architecture.
• Familiarity with FPGA platforms such as Agilex, Stratix, Arria, or Xilinx devices.

Responsibilities

• Develop, generate, and maintain FPGA images for validation platforms.
• Perform FPGA IP validation and functional verification activities.
• Execute validation test plans, regression suites, and debug failures.
• Support FPGA bring-up, image integration, and platform enablement.
• Analyze build failures, validation issues, and root-cause problems.
• Automate build and validation workflows using scripting languages.
• Work with design and verification teams to resolve RTL, firmware, and integration issues.
• Maintain validation documentation, test reports, and debug logs.
• Support continuous integration and automated regression environments.
• Track, reproduce, and verify fixes for reported defects.

Skills

FPGA validation

pre-silicon validation

image generation

build flows

digital design concepts

SoC/IP architecture

debugging

Git

scripting

Education

Bachelor's/Master's in Electronics/EE/CE

Tools

Quartus

Vivado

ModelSim

QuestaSim

Job description

UST seeks an FPGA Validation & Image Build Engineer to support FPGA-based pre-silicon validation activities. The role focuses on FPGA image generation, IP validation, regression execution, and build automation, collaborating with RTL, verification, firmware, and platform teams to ensure FPGA prototypes and IP work before silicon.

The engineer will automate build and validation workflows, analyze failures, and maintain validation docs and logs, contributing to CI/CD environments and defect