Memory Validation Lead - DDR Subsystem Tests & Analysis

UST Malaysia; Seberang Perai; Sur place; MYR 60 000 - 80 000; Plein temps

Résumé du poste

UST Malaysia is seeking a memory validation engineer to lead platform-level memory validation efforts in Penang. You will drive DDR test plans and collaborate closely with silicon design and cross-site memory teams to ensure thorough validation across products.

The role emphasizes hands-on debugging of DDR interfaces, reading schematics, and using Python/Ruby/Perl for automation. Strong communication and program management skills are essential in a fast-paced environment.

Qualifications

• Develop and execute platform level electrical and functional test plans for memory subsystems.
• DDR/GDDR memory test experience on electronic components such as processors is a big plus.
• Extensive hands-on debugging of I/O interfaces such as DDR.
• Ability to read schematics and layout documentation.
• Strong written and oral communication skills.
• Familiar with Python, Ruby, and Perl languages.
• Self-motivated with program management capability.

Responsabilités

• Focus on memory sub-system validation.
• Provide DDR technical leadership in test & validation.
• Develop and execute system level memory sub-system validation test plans across products.
• Collaborate with silicon design and cross-site memory teams on test execution & debugging.
• Work with validation, design, firmware, software, and automation teams for integration and validation.
• Deliver professional project reports and highlight risks with mitigation plans.
• Use data analysis to optimize processes, efficiency, and quality.
• Identify opportunities to improve validation processes and automation.

Connaissances

Memory validation

DDR testing

Platform test plans

Python

Ruby

Perl

I/O interface debugging

Program management

Data analysis

Communication

Formation

BE or MSc in related field

Description du poste

UST Malaysia is seeking a memory validation engineer to lead platform-level memory validation efforts in Penang. You will drive DDR test plans and collaborate closely with silicon design and cross-site memory teams to ensure thorough validation across products.

The role emphasizes hands-on debugging of DDR interfaces, reading schematics, and using Python/Ruby/Perl for automation. Strong communication and program management skills are essential in a fast-paced environment.