Pre-Silicon SoC Memory Validation Engineer

Intel Corporation; Kuala Lumpur; Hybrid; MYR 120,000 - 180,000; Full time

Job summary

Intel Corporation in Penang, Malaysia, is seeking an experienced Memory Pre-sil silicon Validation Engineer. The role focuses on pre-silicon validation, memory subsystem bring-up, and debug across firmware and software interactions.

You will work on enabling memory features for next-generation CPUs/SoCs and perform thorough validation to ensure platform reliability. The candidate will analyze memory initialization, training convergence, and stability, while partnering with architecture, design,

Qualifications

• Bachelor’s degree with 2 years pre-silicon validation or internship experience
• Fundamental knowledge of SoC architectures and PC architecture
• Proficiency in scripting or programming for debugging purposes

Responsibilities

• Perform pre-silicon validation and debug to ensure platform functionality aligns with design specifications
• Develop and enhance debug methodologies, debug flow, and AI debug frameworks to improve efficiency
• Conduct hands-on debug of IP, firmware, and software interaction issues across CPUs, chipsets, boards, and memory subsystems
• Drive memory feature enablement and debug during new-generation CPU/SoC validation, including DDR5 and LPDDR5 bring-up
• Collaborate with architecture, design, firmware, BIOS, and silicon teams to resolve memory-related issues and improve validation coverage

Skills

SoC architecture

Debugging

Scripting

Communication

Education

Bachelor’s degree in a relevant field

Master’s degree in a relevant field

Tools

FPGA

Emulation

FSDB

Job description

Intel Corporation in Penang, Malaysia, is seeking an experienced Memory Pre-sil silicon Validation Engineer. The role focuses on pre-silicon validation, memory subsystem bring-up, and debug across firmware and software interactions.

You will work on enabling memory features for next-generation CPUs/SoCs and perform thorough validation to ensure platform reliability. The candidate will analyze memory initialization, training convergence, and stability, while partnering with architecture, design,