Emulation Engineer

UST Malaysia; Bayan Lepas; On-site; MYR 90,000 - 130,000; Full time

Job summary

UST Malaysia in Bayan Lepas, Penang, is seeking an experienced Design Verification Engineer to verify SoC/IP designs and ensure their correctness. You will develop verification plans, perform simulations, and debug complex issues, collaborating with RTL teams to drive quality.

The role requires strong SystemVerilog/UVM skills, DV methodologies, and hands-on Emulation or FPGA experience, plus proficiency in C/C++ programming. A relevant Bachelor's or Master's degree is required.

Qualifications

• 4+ years of experience in Design Verification.
• Bachelor's/Master's degree in Electrical/Electronic or Computer Engineering.
• Strong experience in SystemVerilog/UVM and DV methodologies.
• Hands-on experience with Emulation or FPGA is preferred.
• Proficiency in C/C++ programming.
• Experience with SoC/IP verification, debugging, and simulation tools.

Responsibilities

• Develop and execute verification plans for SoC/IP designs.
• Perform simulation, debugging, and functional verification.
• Support Emulation/FPGA-based verification.
• Write and debug C/C++ test code.
• Work closely with RTL/design teams to identify and resolve issues.

Skills

SystemVerilog/UVM

DV methodologies

C/C++ programming

Emulation/FPGA-based verification

SoC/IP verification

Debugging

Simulation tools

Education

Bachelor's/Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related field

Tools

Simulation tools

Job description

Responsibilities

• Develop and execute verification plans for SoC/IP designs.


• Perform simulation, debugging, and functional verification.


• Support Emulation/FPGA-based verification.


• Write and debug C/C++ test code.


• Work closely with RTL/design teams to identify and resolve issues.

Requirements

• 4+ years of experience in Design Verification.


• Bachelor's/Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related field.


• Strong experience in SystemVerilog/UVM and DV methodologies.


• Hands-on experience with Emulation or FPGA is preferred.


• Proficiency in C/C++ programming.


• Experience with SoC/IP verification, debugging, and simulation tools.