E-Core CPU Physical Design Engineer – Hybrid in Penang

Intel Corporation; Seberang Perai; Hybrid; MYR 180,000 - 280,000; Full time

Job summary

Intel Corporation in Penang seeks an experienced E-core CPU Physical Design Engineer to participate in design from synthesis through post-layout verification. You will drive constraints for Synthesis/APR tools to meet aggressive timing and power goals while collaborating with micro-architecture, RTL, and circuit teams.

The role requires strong analytic and problem-solving skills and the ability to work independently in a high-performing team with tight schedules.

Qualifications

• BS or MS in Electrical Engineering or Computer Engineering.
• Minimum 5 years in CPU physical design and timing verification.
• Experience with Synthesis/APR flows on multi-voltage high-frequency designs.
• Proficiency in Tcl scripting.
• Floorplanning and physical design and timing closure.
• Formal equivalence, DRC/LVS, IR and electro-migration checks.
• Strong analytical ability and communication skills.
• Ability to work in a high-performance team with aggressive schedules.

Responsibilities

• Logic synthesis and place-and-route for CORE IP blocks.
• Floor-planning and routing studies with block level timing analysis.
• Work on low power techniques and power reduction in sub-systems.
• Physical verification closure of block/sub-system.
• Scripts writing for data analysis and recipe creation.
• Collaborate with micro-architecture, RTL and circuit teams.

Skills

CPU physical design

Timing verification

Synthesis/APR flows

Tcl scripting

Floorplanning

Physical design

Timing closure

Formal equivalence

DRC/LVS

IR analysis

Electro-migration checks

Education

BS or MS in Electrical Engineering or Computer Engineering

Tools

Fusion Compiler

DCT

DCE

ICC2

RedHawk

ICV

Conformal

Calibre

PrimeTime

StarRCXT

Job description

Intel Corporation in Penang seeks an experienced E-core CPU Physical Design Engineer to participate in design from synthesis through post-layout verification. You will drive constraints for Synthesis/APR tools to meet aggressive timing and power goals while collaborating with micro-architecture, RTL, and circuit teams.

The role requires strong analytic and problem-solving skills and the ability to work independently in a high-performing team with tight schedules.