E-core Senior CPU Physical Design Engineer

Intel Corporation; Seberang Perai; Hybrid; MYR 180,000 - 240,000; Full time

Job summary

Intel Corporation in Penang, Malaysia seeks a Senior CPU Physical Design Engineer to drive synthesis, floorplanning, and timing closure for next-gen Atom cores. You will collaborate with RTL, micro-architecture, and circuit teams to optimize performance and power while meeting aggressive schedules in a hybrid work setup.

Requirements include a BS or MS in Electrical or Computer Engineering and 7+ years of CPU physical design experience, with proficiency in Fusion Compiler and PrimeTime.

Qualifications

• Must have BS or MS in Electrical Engineering or Computer Engineering.
• Minimum 7 years of CPU physical design and timing verification experience.
• Experience with Synthesis/APR flows, floorplanning, and timing closure.
• Familiarity with DRC/LVS, IR and electro-migration checks.

Responsibilities

• Perform logic synthesis and place-and-route for CORE IP blocks.
• Conduct floorplanning, routing studies and block-level timing analysis.
• Work on low power techniques and power reduction in sub-systems.
• Physical verification closure of block/sub-system and scripts.
• Collaborate with micro-architecture, RTL and circuit teams to meet targets.

Skills

CPU physical design

Timing verification

Synthesis/APR flows

Tcl scripting

Floorplanning

Physical design

Timing closure

DRC/LVS

Electro-migration checks

IR analysis

Education

BS or MS in Electrical Engineering or Computer Engineering

Tools

Fusion Compiler

DCT

DCE

ICC2

RedHawk

ICV

Conformal

Calibre

PrimeTime

StarRCXT

Job description

## E-core Senior CPU Physical Design EngineerApply: Malaysia, Penang: Full time: Posted Today: JR0287908# **Job Details:**## Job Description:We created the Intel Atom Processor (E-Core), a disruptive technology that enables a broad range of devices including entry PC's, smartphones, modems, 2 in 1 laptops, micro-servers, and other Internet-of-Things IoT devices. You will be part of a team, participating in the design of a future generation high performance Intel Atom microprocessor. This role requires an engineer with strong analytic and problem solving skill, an ability to communicate well, and willing to share and discuss issues. You will work on implementation of CPU Core blocks from synthesis through post-layout verification and tapeout. You will develop the custom constraints for driving synthesis and Auto-Place and Route APR tools to implement and optimize the design to meet aggressive timing and power goals. You will work closely with micro-architecture, RTL, and custom circuit teams to converge the design to project targets.The responsibilities will be tailored to the candidate's skills and expertise and will include several of the following, but not be limited to:* Logic synthesis and place and route for CORE IP blocks.* Performing floor-planning and routing studies and implementation Block/sub-system level timing analysis.* Work on low power techniques and power reduction in sub-system.* Physical verification closure of block/sub-system.* Scripts writing for data analysis and recipe creation.* Strong analytical ability, problem solving and communication skills.* Ability to work independently and at various levels of abstraction.* Strong communication and team work skills.* Capable of working in a high performing team to deliver the results required from the organization.* Ability to work well in at team and be productive under aggressive schedules.* Ability to guide and mentor junior team members.## **Qualifications:**You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum qualifications: Must have either BS or MS in Electrical Engineering or Computer Engineering. Minimum 7 year of experience in:* CPU physical design and timing verification.* Synthesis/APR flows on multi voltage high frequency designs including custom polygon editing.* Tcl scripting.* Noise, cross-talk, OCV analysis.* Floorplanning and physical design and timing closure.* Formal equivalence, DRC/LVS, IR and electro-migration checks. Preferred qualifications:* 9+ years of experience with the above skill sets.* Experience with Fusion Compiler, DCT, DCE, ICC2, RedHawk, ICV, Conformal, Calibre, PrimeTime, StarRCXT.* Cadence Tools Experience Not a Must But Preferred.## Job Type:Experienced Hire## Shift:Shift 1 (Malaysia)## Primary Location:Malaysia, Penang## Additional Locations:## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \\* Job posting details (such as work model, location or time type) are subject to change.