Custom Layout Engineer

Bell Ward Malaysia; Penang; On-site; MYR 90,000 - 150,000; Full time

Job summary

Bell Ward Malaysia is seeking an Analog IC Layout Engineer to support custom analog IP development and full-chip integration. The role involves hands-on layout duties and potential leadership in layout planning.

You will work with TSMC process nodes (7nm/5nm/3nm) and deliver custom Analog and High-Speed Mixed-Signal layouts including HSIO, SerDes, PLLs, VCOs, and Bandgap circuits. Strong EM/IR drop and DRC/LVS sign-off experience is essential.

Qualifications

• 3-12 years of hands-on IC Custom Layout experience, with the ability to work independently or lead layout planning.
• Strong experience with TSMC process nodes, preferably advanced FinFET technologies (7nm, 5nm, or 3nm).
• Proven experience in custom Analog and High-Speed Mixed-Signal layout, including HSIO, SerDes (TX/RX), PLLs, VCOs, and Bandgap circuits.
• Strong knowledge of high-speed layout techniques, parasitic optimization, and sign-off verification, including EM, IR drop, ESD/Latch-up, and DRC/LVS closure.
• Strong English communication skills with the ability to collaborate effectively with circuit design engineers on post-layout (PEX) optimization.

Responsibilities

• Support custom analog IP development and full-chip integration.

Skills

IC Layout

Analog IC

HS SerDes

Sign-off (DRC/LVS)

EM/IR drop

Layout planning

TSMC FinFET

PEX collaboration

English communication

Job description

Our client in semiconductor industry is looking for an Analog IC Layout Engineer to support custom analog IP development and full-chip integration.

• 3-12 years of hands-on IC Custom Layout experience, with the ability to work independently or lead layout planning.
• Strong experience with TSMC process nodes, preferably advanced FinFET technologies (7nm, 5nm, or 3nm).
• Proven experience in custom Analog and High-Speed Mixed-Signal layout, including HSIO, SerDes (TX/RX), PLLs, VCOs, and Bandgap circuits.
• Strong knowledge of high-speed layout techniques, parasitic optimization, and sign-off verification, including EM, IR drop, ESD/Latch-up, and DRC/LVS closure.
• Strong English communication skills with the ability to collaborate effectively with circuit design engineers on post-layout (PEX) optimization.

We thank you for applying with us in advance but only short-listed candidates will be notified.

For candidates who applied to this job is deemed to have consented to the collection, use and disclosure of personal data by our organization for a purpose of this or any job application with Bell Ward.

Company Registration No.: 1080098-P (JTK License No: JTKSM 427)