Analog Mixed Signal Layout Engineer

UST; Penang; On-site; MYR 110,000 - 170,000; Full time

Job summary

UST in Penang is seeking an experienced analog/mixed-signal layout engineer to design full-custom layouts for high-speed SerDes and DDR interfaces, optimizing performance and reliability toward tape-out readiness.

The candidate will use Cadence Virtuoso, perform DRC/LVS/ERC checks, and contribute to ESD, floorplanning, and power delivery tasks across advanced 7nm or below processes, with Samsung 5nm as a strong edge.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering or related field.
• Strong experience in analog and mixed-signal layout design.
• Proficient with Cadence Virtuoso and layout tools.

Responsibilities

• Develop full-custom layouts for analog and mixed-signal circuits.
• Layout SerDes I/O, DDR I/O, and high-speed interfaces.
• Layout PLL, DLL, LDO, Bandgap.
• Design pure analog layouts focusing on matching and performance.
• I/O floorplanning and power delivery planning.
• ESD layouts and ESD analysis support.
• C4 bump and RDL planning and implementation.
• Layout verification: DRC, LVS, ERC; collaborate with teams for tape-out.
• Optimize layouts for performance, area, reliability, manufacturability on advanced nodes.

Skills

Analog layout design

Mixed-signal layout

High-speed I/O layouts

I/O floorplanning

Power delivery planning

ESD layouts

C4 bump & RDL

DRC/LVS/ERC

Cadence Virtuoso

Education

Bachelor's or Master's degree in Electrical/Electronic Engineering

Tools

Cadence Virtuoso Layout Suite

Job description

Responsibilities

• Develop and implement full-custom layout for analog and mixed-signal circuits.
• Perform layout implementation for SerDes I/O, DDR I/O, and other high-speed I/O interfaces.
• Execute layout for PLL, DLL, LDO, Bandgap, and other analog IPs.
• Design and optimize pure analog circuit layouts with a focus on matching, symmetry, and performance.
• Perform I/O floorplanning and power delivery planning to ensure robust design implementation.
• Develop and verify I/O ESD layouts and support ESD analysis.
• Support C4 bump and Redistribution Layer (RDL) planning and implementation.
• Perform layout verification including DRC, LVS, ERC, and collaborate with design, verification, and package teams to achieve successful tape-out.
• Optimize layouts for performance, area, reliability, and manufacturability using advanced process technologies.

Requirements

• Bachelor's or Master's degree in Electrical/Electronic Engineering or a related discipline.
• Strong experience in analog and mixed-signal layout design.
• Hands-on experience in one or more of the following:
  • SerDes I/O, DDR I/O, or other high-speed I/O layouts.
  • PLL and DLL layouts.
  • LDO, Bandgap, and power delivery implementation.
  • Pure analog circuit layout.
  • I/O floorplanning and power delivery planning.
  • I/O ESD layout and analysis.
  • C4 bump and RDL implementation.
• Proficient with Cadence Virtuoso Layout Suite and related physical design/layout tools.
• Strong understanding of DRC, LVS, ERC, parasitic effects, and analog layout best practices.
• Experience with advanced process technologies (7nm or below) is required.
• Experience with Samsung 5nm (or below) layout is a strong advantage.