Custom Layout Engineer

AdoreSys; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

AdoreSys in Penang, Bayan Lepas invites talented Custom Layout Engineers (Junior to Technical Lead) to help shape the next generation of ICs powering tomorrow’s AI breakthroughs. You will own floorplanning, layout construction, physical verification, and QA sign‑off for Standard Cell, Memory, IO/ESD, Analog IP, and RF building blocks, coordinating with multi‑site teams to optimize PPA.

A Bachelor’s degree in Electrical/Electronic or Materials Science Engineering and 2–7 years of hands-on layout

Qualifications

• Bachelor’s degree in Electrical, Electronic, or Material Science Engineering.
• 2–7 years hands-on custom IC layout experience with Standard Cell/Memory/IO/ESD.
• Experience with finFET/GAA process nodes; Analog/RF welcome.
• Strong understanding of DRM, deep sub-micron, DFM issues for high-performance layouts.
• Proficient in debugging DRC/LVS/ERC and PV checks.
• Proficient in Synopsys/Cadence layout editors and PV tools.
• Team player with cross‑team communication and time management.

Responsibilities

• Realize physical implementation including floorplanning, layout construction, PV and QA sign-off.
• Manage complete layout implementation and provide timely project status updates.
• Collaborate with multi-functional and multi-site teams to optimize layout for Power, Performance & Area (PPA).

Skills

DRM CMOS

DFM issues

Physical verification

Teamwork

Layout optimization

Education

Bachelor’s degree in Electrical, Electronic, or Material Science Engineering

Tools

Synopsys/Cadence tools

Job description

Level: Junior/Senior/Staff/Technical Lead

Overview:

Are you passionate about driving innovation in microchip design? Ready to take the lead in shaping the next generation of integrated circuits? We’re looking for a variety of positions for Custom Layout Engineer to join our team and make a significant impact on advanced semiconductor technology—including the chips powering tomorrow’s AI breakthroughs.

What you’ll do:

• Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
• Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning, layout construction, physical verification and QA flow sign-off.
• Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project.
• Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area (PPA).

Who we’re looking for:

• Bachelor’s degree in Electrical, Electronic, or Material Science Engineering.
• More than 2~7 years of hands-on experience in custom IC layout for Standard Cell, Memory Compiler or IO/ESD libraries using advanced finFET/GAA process nodes; candidates with Analog/RF experiences are welcomed to apply.
• Proficient in understanding DRM of advanced CMOS technologies and have a good grasp of deep sub-micron and DFM issues for high-performance layout designs.
• Analytical and skillful in debugging physical verification checks (eg. DRC/LVS/ERC, etc.).
• Proficient in Synopsys/Cadence layout editor and physical verification tools.
• Team player and effective in cross-team communication and time management.
• Experienced candidate will be considered for senior position.