IC Custom Layout Engineer — Shape Next‑Gen Chips

AdoreSys; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

AdoreSys in Penang, Bayan Lepas invites talented Custom Layout Engineers (Junior to Technical Lead) to help shape the next generation of ICs powering tomorrow’s AI breakthroughs. You will own floorplanning, layout construction, physical verification, and QA sign‑off for Standard Cell, Memory, IO/ESD, Analog IP, and RF building blocks, coordinating with multi‑site teams to optimize PPA.

A Bachelor’s degree in Electrical/Electronic or Materials Science Engineering and 2–7 years of hands-on layout

Qualifications

• Bachelor’s degree in Electrical, Electronic, or Material Science Engineering.
• 2–7 years hands-on custom IC layout experience with Standard Cell/Memory/IO/ESD.
• Experience with finFET/GAA process nodes; Analog/RF welcome.
• Strong understanding of DRM, deep sub-micron, DFM issues for high-performance layouts.
• Proficient in debugging DRC/LVS/ERC and PV checks.
• Proficient in Synopsys/Cadence layout editors and PV tools.
• Team player with cross‑team communication and time management.

Responsibilities

• Realize physical implementation including floorplanning, layout construction, PV and QA sign-off.
• Manage complete layout implementation and provide timely project status updates.
• Collaborate with multi-functional and multi-site teams to optimize layout for Power, Performance & Area (PPA).

Skills

DRM CMOS

DFM issues

Physical verification

Teamwork

Layout optimization

Education

Bachelor’s degree in Electrical, Electronic, or Material Science Engineering

Tools

Synopsys/Cadence tools

Job description

AdoreSys in Penang, Bayan Lepas invites talented Custom Layout Engineers (Junior to Technical Lead) to help shape the next generation of ICs powering tomorrow’s AI breakthroughs. You will own floorplanning, layout construction, physical verification, and QA sign‑off for Standard Cell, Memory, IO/ESD, Analog IP, and RF building blocks, coordinating with multi‑site teams to optimize PPA.

A Bachelor’s degree in Electrical/Electronic or Materials Science Engineering and 2–7 years of hands-on layout