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UST is seeking an experienced hardware test engineer to develop and maintain ATE test programs and patterns. You will collaborate with IP design teams to validate test content during silicon bring-up and characterize silicon across diverse conditions.
The role requires strong programming/scripting skills (C, C++, Java, Python, etc.), familiarity with version control, and knowledge of JTAG/BIST/HSIO. Windows/Linux/Unix experience is expected.
1. Partner with IP design, validation, and architecture teams to ensure comprehensive IP content coverage, and to develop, validate, and debug test patterns.
2. Build and maintain test program infrastructure, leveraging the latest Best Known Methods.
3. Evaluate and validate new product features, test conditions, methodologies, and test content during initial silicon bring-up.
4. Conduct silicon characterization across various process, voltage, and temperature conditions.
5. Correlate and release test programs for high-volume production environments.
6. Lead initiatives to improve Key Performance Indicators, focusing on reducing test time, debugging yield issues, and enhancing product quality.
7. Provide support for product qualification processes and assist in debugging customer returns.
PREFERRED EXPERIENCE:
1. Hands-on experience developing ATE test programs and patterns, with a preference for Advantest 93K platforms.
2. Understanding of JTAG, BIST, and HSIO concepts.
4. Strong programming and scripting skills in languages such as C, C++, Java, Ruby, Perl, or Python.
5. Familiarity with version control systems.
6. Competence in statistical analysis techniques.
7. Proficiency in Windows, Unix, and Linux operating systems.
8. Solid understanding of modern computer architecture.