AMS Circuit Design Engineer

UST; Penang; On-site; MYR 180,000 - 240,000; Full time

Job summary

UST in Penang, Malaysia, is seeking an experienced analog/mixed-signal IC design engineer to drive high-performance circuit development for advanced SoCs. You will design SerDes/DDR interfaces, PLL/DLLs, and clock distribution, while developing LDOs and power delivery models.

The role requires hands-on Cadence Virtuoso/ADE work, analog RTL modeling, and proven capability to verify complex analog blocks in a collaborative, multi-disciplinary environment.

Qualifications

• Experience in analog and mixed-signal IC design required.
• Proficiency with Cadence Virtuoso and ADE tools.
• Hands-on in SerDes I/O, DDR I/O, PLL/DLL, and clock distribution.
• Experience with 7nm or below process technologies is required.
• Experience with Samsung 5nm layout is a strong advantage.

Responsibilities

• Design and develop high-performance analog and mixed-signal circuits for advanced SoCs.
• Design and optimize high-speed I/O interfaces such as SerDes I/O, DDR I/O, or other high-speed interfaces.
• Design and validate PLL, DLL, and high-speed clock distribution circuits.
• Develop power management circuits including LDO, Bandgap Reference, and power delivery simulations.
• Design, simulate, and verify analog circuits; perform analog timing analysis.
• Develop analog behavioral/RTL models and perform analog timing analysis.

Skills

Analog design

Mixed-signal

High-speed I/O

Clock distribution

Power management

RTL modeling

Analog timing

Debugging

Education

Bachelor's/Master's/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Cadence ADE

Job description

• Design and develop high-performance analog and mixed-signal circuits for advanced SoCs.
• Design and optimize high-speed I/O interfaces such as SerDes I/O, DDR I/O, or other high-speed interface circuits.
• Design and validate PLL, DLL, and high-speed clock distribution circuits.
• Develop power management circuits including LDO, Bandgap Reference, and perform power delivery simulations.
• Design, simulate, and verify both simple and complex analog circuits.
• Develop analog behavioral/RTL models and perform analog timing analysis.
• Perform schematic design, simulation, verification, and debugging using Cadence Virtuoso, ADE, and related EDA tools.
• Collaborate with layout, verification, and system teams to achieve design closure and silicon success.

Requirements

• Bachelor's, Master's, or PhD in Electrical/Electronic Engineering or related field.
• Strong experience in analog and mixed-signal IC design.
• Hands-on experience in one or more of the following:
• SerDes I/O, DDR I/O, or other high-speed I/O interfaces.
• PLL, DLL, and high-speed clock distribution.
• LDO, Bandgap Reference, and power delivery simulation.
• Pure analog and complex analog circuit design.
• Experience with analog RTL modeling and analog timing analysis.
• Proficient with Cadence Virtuoso, ADE, and other analog design/simulation tools.
• Experience in advanced process technologies 7nm or below is required.
• Experience with Samsung 5nm (or below) layout is a strong advantage.
• Strong analytical, debugging, and problem-solving skills with the ability to work in a collaborative environment.