AI-Driven RTL/DV Engineer for Silicon Design

UST; Seberang Perai; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST in Malaysia seeks an engineer with ASIC/SoC RTL Design Verification or RTL Design experience and hands-on GenAI/LLM expertise to build AI-powered solutions that improve silicon design, verification, debug, and productivity workflows.

The role involves developing RTL and UVM environments, debugging IP/SoC issues, and creating AI copilots for RTL, DV, and automation, leveraging LLMs for test and coverage analysis and driving AI adoption across silicon teams.

Qualifications

• 3+ years in ASIC/SoC RTL Design and/or Design Verification
• Strong Verilog/SystemVerilog, UVM, SVA, functional coverage, and debug skills
• 1+ year of practical GenAI/LLM experience
• Strong Python, Linux, Git, and automation scripting
• Experience with AI frameworks such as LangChain, LangGraph, AutoGen, CrewAI, MCP, or RAG
• Familiarity with ASIC/SoC development flows and EDA tools

Responsibilities

• Develop RTL and/or UVM-based verification environments
• Debug IP, subsystem, and SoC-level issues
• Build AI agents and copilots for RTL, DV, debug, code review, and automation
• Apply LLMs for test generation, assertion generation, coverage analysis, and root-cause analysis
• Develop AI workflows using Python, RAG, vector databases, and GenAI platforms
• Drive AI adoption and productivity improvements across silicon engineering teams

Job description

UST in Malaysia seeks an engineer with ASIC/SoC RTL Design Verification or RTL Design experience and hands-on GenAI/LLM expertise to build AI-powered solutions that improve silicon design, verification, debug, and productivity workflows.

The role involves developing RTL and UVM environments, debugging IP/SoC issues, and creating AI copilots for RTL, DV, and automation, leveraging LLMs for test and coverage analysis and driving AI adoption across silicon teams.