SoC Infrastructure/NoC, Power & Performance Validation Engineer, Staff

North American Production Sharing, Inc.; Tijuana; Presencial; MXN 900.000 - 1.200.000; Jornada completa

Descripción de la vacante

North American Production Sharing, Inc. is seeking a Staff SoC Infrastructure/NoC, Power & Performance Validation Engineer to join the SVE team.

You will work on end-to-end silicon validation across pre- and post-silicon phases, developing, validating, and scaling system-level test content for Next-Generation Premium SoCs. The ideal candidate has deep understanding of digital design, on-chip interconnects, NoCs, AXI/AHB, and memory hierarchies, with strong C/C++, Python, and assembly skills.

Formación

• BS/MS/PhD in Electrical/Computer Science or related field with 4+ years in ASIC design, verification, validation, integration, or related work.
• Strong C/C++/Python skills and experience in embedded systems and drivers.
• Experience with pre- and post-silicon validation, performance and power analysis, and system-level debug.

Responsabilidades

• Develop, validate, and scale system-level test content across HW/SW boundaries.
• Create performance validation plans; analyze bandwidth, QoS, latency, and throughput.
• Evaluate AI inference workloads for throughput, latency, memory bandwidth, and power efficiency.
• Contribute to methodology for benchmarking and KPI tracking across generations.
• Create dashboards and technical reviews for leadership and cross-functional stakeholders.

Conocimientos

C

C++

Python

Assembly

Embedded systems

Debugging

Power/Performance validation

SoC validation

Educación

Bachelor's degree in Science or Engineering

Master's degree in Science or Engineering

PhD in Science or Engineering

Herramientas

Perfmon

JTAG debuggers

Kernel debuggers

Emulation platforms

Descripción del empleo

SoC Infrastructure/NoC, Power & Performance Validation Engineer, Staff

Tipo de empleo: Permanent

Tipo jornada: Full-time

Fecha de publicación: 05-10-2026

Identificador oferta: 62604

General Summary:

System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases.

This role focuses on content quality and system-level validation enablement, offering deep exposure to SoCs through bare-metal validation content, scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content, ensuring high-quality silicon validation across a wide range of SoC domains.

Excellent Opportunity to work on cutting-edge SoCs across multiple product segments, including:

• Premium mobile and flagship platforms
• AI Accelerator platform

Role Overview:

The team is currently seeking candidate specifically forSOC Infrastructure/NoC, Power and Performance Validationin pre-silicon emulation and post-silicon of industry-leading, next generation Premium-Tier Mobile & AI Accelerator platform.An ideal candidate is expected to have an excellent understanding of digital design fundamentals, on-chip interconnects, writing content to validate and analyze SOC bus architecture,performance and power.

• Come up with thorough performance validation plans and work closely with team members to ensure Performance-Power trade-offs are factored in
• SOC Bandwidth, QoS, Latency and Throughput analysis
• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 5+ years of experience in silicon validation, or platform bring-up.
• Interconnect architectures - NoCs, AXI, AHB etc. Knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverage
• Solid expertise in various FIFO designs and related performance/functionality aspects
• Memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, MTE, MPAM
• Thorough understanding of CPU and DDR concepts, Multimedia, GPU, Peripherals
• Systemlow power modes, Dynamic clock and voltage scaling operations, Interrupt architecture
• Debug architecture - interactions with JTAG based debuggers, state dump scripts
• In depth debugging experience for Complex HW and SW issues
• Experience working with Perfmon architecture -performance counters, telemetry data, and hardware/software co-optimization.
• Drive correlation between pre-silicon models, emulation platforms, and silicon performance measurements.
• Evaluate AI inference and training workloads to ensure optimal throughput, latency, memory bandwidth, and power-performance efficiency.
• Contribute to methodology development for performance characterization, benchmarking, and KPI tracking across product generations.
• Create performance dashboards, reports, and technical reviews for leadership and cross-functional stakeholders.
• Experience in embedded systems/expertise in C, C++, Python and assembly languages. Design and Implementation of drivers and test content
• Logical thinking and problem-solving ability with focus on Power, Performance and SoC System feature validation
• Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design
• Familiarity in debug tools including JTAG and kernel debuggers

Preferred Qualification:

• Strong understanding of computer architecture, AI/ML accelerators, memory hierarchy, cache coherency, and on-chip interconnects.
• Knowledge of AI/ML workloads, tensor operations, matrix multiplication, transformer models, and large-scale inference systems.
• Familiarity with System level debug, silicon bring-up

Minimum Qualifications:

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.