SOC Clock & Power Management Validation Engineer, Staff

QUALCOMM, Inc.; Tijuana; Presencial; MXN 1.647.000 - 2.379.000; Jornada completa

Descripción de la vacante

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA seeks a System Validation Engineer to drive clock, power, reset, and PMIC validation for next-gen Premium MSM platforms, spanning pre- and post-silicon.

You will partner with Architecture, Design, Verification and Firmware teams to debug power, performance, stability, and scalability issues, define validation methodologies, stress workloads, and deliver production-quality silicon across program milestones.

Formación

• Bachelor's degree in engineering (electronics, computer engineering, or related)
• 4+ years in ASIC design/validation/verification/integration
• Experience in clock/power validation and SoC validation
• Proficient in C and Python; strong debugging skills

Responsabilidades

• Own E2E bare metal framework validation of SoC clock and power architectures
• Develop test plans and validate design changes at pre- and post-silicon stages
• Create scalable device drivers and standalone/system tests in C
• Automate validation using Python/Perl/Shell; use lab instruments for measurements
• Collaborate with Architecture, Design, Verification and Firmware teams

Conocimientos

C

Python

JTAG

problem solving

debugging

Educación

Bachelor's degree in Engineering

Master's degree in Engineering or related field

PhD in Science/Engineering (advantage)

Herramientas

Lab instruments

Cross-Compilers/Linkers/Makefiles

Descripción del empleo

Company:

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm's System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre-and post-silicon phases.

Excellent Opportunity to work on cutting-edge SoCs across multiple product segments, including:

• Premium mobile and flagship platforms
• Data center
• AI Accelerator platform

Role Overview:

System level validation of clock, power, reset, and power-management architectures for next-generation Premium Tier MSM platforms. Drive pre-silicon and post-silicon validation of Clocking infrastructure, PMIC integration, DVFS, and low-power features across complex multi-die AI systems. Partner closely with Architecture, Design, Verification & Firmware teams to debug and root-cause power, performance, stability, and scalability issues. Define validation methodologies, stress workloads, and automation frameworks to ensure robust operation under demanding AI training and inference scenarios. Own power subsystem bring-up readiness and delivery of production-quality silicon across all program milestones

An ideal candidate combines expertise in Clocking, DVFS, Power Management, PMIC, Firmware, Silicon Bring-up, and AI/HPC platform validation

Roles & Responsibilities:

• Own the E2E bare metal framework validation SoC clock and power architectures
• Validation planning – understand design changes, visualize standalone and system level test requirements and scenarios
• Test plan development – clearly document test strategy and dependencies
• Conduct validation strategy and test plan review with all stakeholders – architects, designers, verification engineers, software engineers
• Develop scalable device drivers, standalone and system tests using C
• Debug complex issues both on pre-Si and post-Si platforms, provide debug direction
• Review validation platform schematics to ensure post-Si debug support – might have to work with platform design team
• Automate validation process – development, execution, inference using python, perl, shell
• Use lab instruments – multimeter, oscilloscopes, logic analyzer
• Efficiently collaborate with teams in different time zones – both internal and external

Minimum Requirements:

• Bachelor's degree in engineering (electronics, computer engineering etc.)
• 5+ years of relevant experience in SoC validation and / or associated areas (SW development, embedded systems etc.)
• Prior work experience in clock/ power validation
• Proficient in C, Python
• Experienced in using lab instruments – multimeter, oscilloscopes, logic analyzers
• Exposure to debug tools (JTAG etc.). Knowledge of debug methodology of ARM based SoCs
• Very good at problem solving - analytical and debugging skills

Preferred Qualifications:

• Prior exposure to below SW skills would add an edge above other applicants:
  • Experience with Cross-Compilers, Linkers and makefiles
  • Understanding of coherency and concurrency in modern SoC architecture
• Knowledge of PMIC/ prior experience in validating rail power (power measurement tools/ setups)
• Knowledge of pre-Silicon validation and debug on FPGA based emulation platforms is a plus
• Knowledge of RTL and HDLs (Verilog/ System Verilog) would be an additional advantage
• Should have prior work experience in a cross functional matrix work environment

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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