Silicon Design Intern — Flows & Methodology (Hybrid)

Intel Corporation

Región Centro

Hybrid

MXN 134,000 - 201,000

Full time

14 days+

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Job summary

Intel Corporation in Mexico is offering a Silicon Design – Flows and Methodology Intern position. You will help develop and document tools, flows, and methodologies for silicon design, analyze efficiency, and support automation across projects.

The role emphasizes collaboration with cross-functional teams, hands-on project work, and opportunities to learn while contributing to Intel’s IP design initiatives. Fluency in English is expected, with work authorization in Mexico.

Qualifications

  • Pursuing a technical BS with at least one year remaining.
  • 6+ months hands-on experience with Python and Unix.
  • Foundational knowledge of IC design flows and microarchitecture.
  • Familiarity with RTL Design and SystemVerilog.
  • Understanding of tools, flows, and methodology (TFM) development.
  • Advanced English and unrestricted work authorization in Mexico.

Responsibilities

  • Assist in developing and documenting silicon design tools, flows, and methodologies.
  • Analyze design efficiency and identify quality gaps to drive improvements.
  • Support automation and scalability across multiple design projects.
  • Collaborate with cross-functional teams to contribute to internal tool development and enablement.
  • Participate in hands-on projects aligned with Intel's business goals.

Skills

Problem solving
Communication
Execution discipline
Continuous learning

Education

BS in Electrical/Computer Engineering or related field (1 year remaining)

Tools

Python
Unix
SystemVerilog
RTL Design

Job description

Intel Corporation in Mexico is offering a Silicon Design – Flows and Methodology Intern position. You will help develop and document tools, flows, and methodologies for silicon design, analyze efficiency, and support automation across projects.

The role emphasizes collaboration with cross-functional teams, hands-on project work, and opportunities to learn while contributing to Intel’s IP design initiatives. Fluency in English is expected, with work authorization in Mexico.

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