Senior Test Engineer — Hardware Automation & Diagnostics

Cadence Design Systems; Región Centro; Presencial; MXN 1.556.000 - 2.196.000; Jornada completa

Descripción de la vacante

Cadence Design Systems seeks a Senior Test Engineer to join a high-energy team ensuring reliable performance of advanced silicon designs. The role focuses on modular hardware diagnostics, test automation across Linux workstations, and cross-functional collaboration with contract manufacturers.

Strong Python, board schematics reading, and ASIC/FPGA experience are required. The position reports to the Director of Test Engineering, with location primarily Guadalajara, Mexico, Cadence offices, or

Formación

• BA/BS degree in Computer Science or Electrical Engineering or equivalent.
• Excellent communication and documentation skills.
• Python scripting and Unix/Linux/shell scripting experience.
• Familiarity with SERDES, ASICs, FPGAs, DDR3/4, I2C, SPI, ENET switches/devices, PCIe.
• Experience with AI coding agents (Claude Code, Cursor, Copilot, Codex).
• Experience with liquid-cooled computer systems is highly desirable.

Responsabilidades

• Interface with CMs and Production Engineers to setup and support automated system testing and board Test Cells.
• Extend the company’s automated tests platform and assist in next-gen improvements including a GUI for test execution and result review.
• Maintain and extend functional diagnostics and APIs using modular design to test HW.
• Maintain and extend automation of Linux workstation setup.

Conocimientos

Python scripting

Board schematics

ASIC testing

Test automation

GUI development

Linux environment

Cross-functional collaboration

Self-starter

Educación

BA/BS in Computer Science or Electrical Engineering

Herramientas

Git

Unix/Linux tools

CI/CD tools

Descripción del empleo

Cadence Design Systems seeks a Senior Test Engineer to join a high-energy team ensuring reliable performance of advanced silicon designs. The role focuses on modular hardware diagnostics, test automation across Linux workstations, and cross-functional collaboration with contract manufacturers.

Strong Python, board schematics reading, and ASIC/FPGA experience are required. The position reports to the Director of Test Engineering, with location primarily Guadalajara, Mexico, Cadence offices, or