Una candidatura hecha para este puesto de trabajo — un currículum y una carta de presentación adaptados que responden directamente a la oferta.
Cadence Design Systems seeks a Senior Test Engineer to join a high-energy team ensuring reliable performance of advanced silicon designs. The role focuses on modular hardware diagnostics, test automation across Linux workstations, and cross-functional collaboration with contract manufacturers.
Strong Python, board schematics reading, and ASIC/FPGA experience are required. The position reports to the Director of Test Engineering, with location primarily Guadalajara, Mexico, Cadence offices, or
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Senior Test Engineer must have the ability to be part of a focused, high-energy team that works collaboratively in a demanding environment to solve challenging issues to ensure excellent reliability of a complex, cutting-edge system provided by industry leading silicon design companies. The Senior Test Engineer be disciplined in building modular, sustainable Hardware diagnostic solutions that use automation to enable user friendly interfaces and output that is human readable and ready for import into automated test tracking and metrics dashboards. You must be able to drive solutions from rough requirements, be innovative, and work cross-functionally and with contract manufacturers to achieve team goals. You must be proficient in Python, know how to read board schematics, have designed board functional tests, have worked with testing ASICs, and have a mindset to level up Production test processes. The ideal candidate should also be a self-starter that intuitively understands how to find solutions to complex problems given a set of constraints. Position reports to: Director of Test Engineering Location: Primarily Guadalajara, Mexico in Cadence office or assigned local partner contract manufacturer sites, or any other locations as assigned or instructed by the Company.
Ingeniero de pruebas sénior El ingeniero de pruebas sénior debe tener la capacidad de formar parte de un equipo enfocado y enérgico que trabaje en colaboración en un entorno exigente para resolver problemas desafiantes a fin de garantizar la excelente confiabilidad de un sistema complejo y de vanguardia proporcionado por compañías de diseño de silicio líderes en la industria. El ingeniero sénior de pruebas debe estar instruido en la creación de soluciones de diagnóstico de hardware modulares y sostenibles que utilicen la automatización para permitir interfaces y resultados fáciles de usar que sean legibles por humanos y estén listos para importarse a paneles de métricas y seguimiento de pruebas automatizados. Debe ser capaz de impulsar soluciones de requisitos difíciles, ser innovador y trabajar de manera interfuncional y con fabricantes contratados para lograr los objetivos del equipo. Debe tener un buen dominio de Python, saber leer los diagramas esquemáticos de placa, haber diseñado pruebas funcionales de placa, haber trabajado con pruebas ASIC y tener una mentalidad de subir el nivel de los procesos de prueba de producción. El candidato ideal también debe ser un emprendedor que comprenda intuitivamente cómo encontrar soluciones a problemas complejos dada una serie de limitaciones. El puesto es subordinado directo de: Director de Ingeniería de pruebas Ubicación: principalmente en Guadalajara, México, en la oficina de Cadence o en los sitios del fabricante por contrato asociado local asignado, o en cualquier otra ubicación asignada o indicada por la Compañía.
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