Senior High-Speed IO & DDR Test Engineer

QUALCOMM, Inc.; Tijuana; On-site; MXN 420,000 - 640,000; Full time

Job summary

QUALCOMM Semiconductores y Sistemas Avanzados de Baja California seeks a Post Silicon Engineer to lead test methodology development and characterization of High Speed SERDES interfaces (PCIe, USB3, UFS, DP, MIPI) and related LP‑DDR/PC‑DDR subsystems.

You will perform silicon bring‑up, debug power and signal integrity issues, coordinate with IC Design, Systems Engineering and Customer Engineering to resolve complex RMA problems, and analyze parametric data to optimize designs across conditions.

Qualifications

• Experience with high-speed test and characterization of SERDES and interfaces.
• Understanding of eye diagrams, jitter and signal integrity analysis.
• Experience with DDR/LPDDR protocols is a plus.
• Hands-on lab experience with test equipment and failure analysis.
• Strong communication and documentation skills.

Responsibilities

• Define and execute test methodologies for high-speed SERDES interfaces.
• Characterize LP-DDR/PC-DDR subsystems and related IOs.
• Lead first silicon bring-up and debug to qualify designs at external foundries.
• Analyze parametric data and optimize design parameters under varying conditions.
• Collaborate with IC Design, Systems Engineering, and Customer Engineering on issues and RMAs.

Skills

High Speed SerDes

DDR protocol knowledge

Lab equipment

Python/C# for test automation

English fluency

VLSI knowledge

Signal integrity

Debugging

Education

Bachelor's degree in Engineering, Computer Science, or related field

Master's degree in Electrical/Electronics Engineering, Computer Science, or related field

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Tools

J-BERT

Oscilloscopes

TDRs

VNAs

Job description

QUALCOMM Semiconductores y Sistemas Avanzados de Baja California seeks a Post Silicon Engineer to lead test methodology development and characterization of High Speed SERDES interfaces (PCIe, USB3, UFS, DP, MIPI) and related LP‑DDR/PC‑DDR subsystems.

You will perform silicon bring‑up, debug power and signal integrity issues, coordinate with IC Design, Systems Engineering and Customer Engineering to resolve complex RMA problems, and analyze parametric data to optimize designs across conditions.