HSIO/DDR Bench Test Engineer

Qualcomm; Tijuana; Presencial; MXN 480.000 - 660.000; Jornada completa

Descripción de la vacante

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA is seeking a Post Silicon Engineering specialist to develop test methodologies and characterize high-speed interfaces (SERDES, PCIe, USB3, UFS, MIPI, LP‑DDR/PC‑DDR). You will drive first-silicon bring-up, debug, and data analysis across conditions, collaborating with IC design and systems teams to resolve complex issues.

Responsibilities include validating electrical compliance, assisting in power integrity and signal integrity,

Formación

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• English fluent (>95% verbal and written).
• 1+ year of experience in related areas preferred.
• Strong verbal and written communication skills.
• Strong organization and documentation skills.
• Strong problem-solving & debugging skills.
• Ability to work independently with initiative to overcome technical challenges.
• Strong interpersonal and teamwork skills in a fast-paced, multi-disciplinary environment.

Responsabilidades

• Define and execute development of test methodologies for high-speed SERDES interfaces.
• Characterize interfaces such as PCIe, USB3, UFS, DP, MIPI, PLLs, LP-DDR & PC-DDR subsystems.
• Drive first-silicon bring-up & debug to qualify designs at external foundries.
• Analyze parametric data across operating conditions to optimize designs.
• Assist with HW design and debug of PI/SI issues related to package and board.

Conocimientos

English fluency

Strong communication

Strong organization

Problem solving

Independent work

Teamwork

Multi-disciplinary teamwork

Educación

Bachelor's degree in CS/EE/Engineering

Herramientas

Python

C#

Oscilloscopes

TDRs/VNAs

J-BERT

Descripción del empleo

Company

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

This position is for the Post Silicon Engineering group that develops test solutions for highly integrated SOCs (System on Chip). Main responsibilities include defining and executing the development of test methodologies and characterization of high‑speed SERDES interfaces such as PCIe, USB3, UFS, DP, MIPI (DSI, CSI), PLLs, and leading‑edge LP‑DDR & PC‑DDR subsystem components (DRAM, DRAM controller, mixed‑signal PHY IP, I/Os, clocking architecture, delay circuits, power distribution network) as well as other proprietary interfaces. Responsibilities include developing and executing characterization plans for high‑speed interfaces to optimize design parameters and validate electrical compliance, driving corresponding first‑silicon bring‑up & debug to qualify designs fabricated at external foundries, and performing technical data analysis of parametric performance over various operating conditions and configurations. The engineer will also assist in HW design and debug power integrity (PI) and signal integrity (SI) issues related to package and board design. The engineer will work closely with cross‑functional teams such as IC design, systems engineering for chip/circuit bring‑up and debug, and with customer engineering and hardware applications teams to resolve customer issues/RMA debug in a time‑critical environment. The individual selected for the position should be passionate about delivering quality work products, seek to continually learn about new products, and possess essential knowledge of industry trends, competitor products, and advances in various engineering fields from publicly available information, assisting in conducting specialized analyses (e.g., feasibility studies, signal integrity, teardown analyses).

Minimum Qualifications

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field.
• English fluent (>95% verbal and written).
• 1+ year of experience in related areas preferred.
• Strong verbal and written communication skills.
• Strong organization and documentation skills.
• Strong problem‑solving & debugging skills.
• Ability to work independently with initiative to overcome technical challenges.
• Strong interpersonal and teamwork skills with proven ability to work effectively in a fast‑paced, multi-disciplinary environment.

Preferred Qualifications

• Master’s degree in Electrical/Computer Engineering or a related field.
• Good understanding of VLSI technologies, CMOS analog and digital integrated circuits, mixed‑signal and semiconductor physics.
• Knowledge of high‑speed test and characterization, including eye diagram characteristics, differential signals, jitter analysis, signal integrity, etc.
• Familiarity with SERDES characterization/validation and transmitter/receiver design blocks.
• Familiarity with DDR 2/3/4/5, LPDDR 2/3/4/5 protocols, timing diagrams, and device specifications.
• Hands‑on experience with lab equipment such as oscilloscopes, TDRs/VNAs, J‑BERT, etc.
• Experience with Python/C# for test automation.
• Familiarity with board‑design concepts (schematic reviews, layout best practices, etc.).
• Good ASIC device‑level characterization skills.
• System‑level knowledge.
• Strong verbal and written communication skills and good organization and documentation skills.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability‑[e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

If you would like more information about this role, please contact Qualcomm Careers.