Senior HBM Layout Engineer for AI & HPC

Micron Technology, Inc; Tlaquepaque; Híbrido; MXN 600.000 - 900.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical plans

Dental plans

Vision plans

Paid time off

Paid holidays

Descripción de la vacante

Micron Technology, Inc in Mexico is seeking a Semiconductor Design Engineer 3 within the HBM layout team to drive the physical implementation of analog, mixed-signal, and digital blocks for cutting-edge memory products.

You will collaborate with global teams, perform layout verification, and push for high quality, performance, and schedule adherence using Cadence Virtuoso and Calibre, while applying AI-assisted workflows.

Formación

• Bachelor's or Master's degree in Electrical Engineering or related field.
• 5+ years of analog/custom layout development using CMOS technologies (planar and FinFET).
• Proficiency in Cadence Virtuoso and Mentor Calibre for DRC/LVS and verification.
• Experience laying out PLLs, ADCs/ DACs, LDOs, bandgaps, charge pumps and related blocks.
• Strong knowledge of analog layout fundamentals, matching and reliability considerations.

Responsabilidades

• Build high-quality analog, mixed-signal, and full-chip layouts for HBM products.
• Conduct physical verification (DRC, LVS, antenna checks) and quality reviews.
• Lead layout planning, area estimation, scheduling, and multi-project execution.
• Collaborate with global teams to resolve layout challenges and optimize performance.
• Apply AI-enabled tools to improve layout efficiency and productivity.

Conocimientos

Analog layout

Mixed-signal design

Layout verification

DRC/LVS checks

PM/leadership

Educación

Bachelor's or Master's in Electrical Engineering

Herramientas

Cadence Virtuoso

Mentor Calibre

Descripción del empleo

Micron Technology, Inc in Mexico is seeking a Semiconductor Design Engineer 3 within the HBM layout team to drive the physical implementation of analog, mixed-signal, and digital blocks for cutting-edge memory products.

You will collaborate with global teams, perform layout verification, and push for high quality, performance, and schedule adherence using Cadence Virtuoso and Calibre, while applying AI-assisted workflows.