Senior ASIC/SoC Verification Architect

HCL Technologies Limited

Guanajuato

In loco

MXN 600.000 - 900.000

Tempo pieno

5 giorni fa

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Descrizione del lavoro

HCL Technologies Limited invites a senior ASIC/SoC verification engineer with 8–14 years of hands-on experience to join our design verification team. You will participate in multiple tapeouts, develop UVM-based testbenches, write test plans, drive functional coverage, and debug complex simulations to ensure design quality.

The role requires strong SystemVerilog, Verilog, UVM expertise, and collaboration with hardware teams.

Competenze

8 to 14 years of experience in ASIC/SoC design and verification
Experience writing ASIC/SoC testplans
Hands-on experience with UVM-based testbench development
Experience building reusable block-level and sub-system testbenches using SystemVerilog and UVM
SV functional coverage and assertions coding
C based TB development for SOC
Writing, executing, and debugging constrained-random and directed test cases
Debugging complex simulation failures using waveform viewers
Collaboration with hardware design teams to resolve bugs and document results

Mansioni

Develop and maintain TB components for SOC with C, SV
Create functional coverage and SVA assertions, analyze code coverage
Set up and debug regression tests, including constrained-random and directed tests
Build reusable block-level/testbench architectures using SystemVerilog/UVM
Perform gate-level simulations and regression analysis
Collaborate with hardware team to document designs and verify test plans
Automate regression tests using scripting (Perl/Shell/Python)