Junior ASIC Physical Design Engineer

Semtech; Aguascalientes; On-site; MXN 250,000 - 420,000; Full time

Job summary

Semtech is seeking an ASIC/Layout Design Engineer 1 to support basic physical design and layout activities for our semiconductor projects. You will help with layout of standard cells, memory blocks, and basic circuit elements, and assist DRC/LVS verification and data preparation for manufacturing.

You will work with EDA tools, contribute to design kit updates, and participate in technology migrations while developing knowledge of semiconductor fabrication rules and layout practices.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• 0-2 years of experience in ASIC layout, physical design, or related role
• Basic knowledge of semiconductor design and layout principles
• Experience with EDA tools and design environments
• Familiarity with IC layout verification preferred

Responsibilities

• Layout Design Support: support physical layout of standard cells, memory blocks, and basic circuit elements.
• Physical Verification Support: assist with DRC/LVS verification and issue resolution.
• Layout Data Preparation: prepare layout data for manufacturing and mask data generation.
• Design Tool Support: assist with design kit implementation and updates, tool setup and configuration.
• Technology Migration Support: assist with porting designs to new process technologies.
• Technical Learning and Development: develop understanding of physical design principles and methodologies.

Skills

ASIC layout

Physical design

EDA tools

Layout verification

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

EVB/EDA environments

Job description

Semtech is seeking an ASIC/Layout Design Engineer 1 to support basic physical design and layout activities for our semiconductor projects. You will help with layout of standard cells, memory blocks, and basic circuit elements, and assist DRC/LVS verification and data preparation for manufacturing.

You will work with EDA tools, contribute to design kit updates, and participate in technology migrations while developing knowledge of semiconductor fabrication rules and layout practices.