HBM Layout Lead for AI & HPC Solutions

3050 Micron Semiconductor Mexico, S.de R.L. de C.V.; Región Centro; Presencial; MXN 700.000 - 1.000.000; Jornada completa

Descripción de la vacante

Micron Technology seeks a Layout Design Staff Engineer for its HBM team in Guadalajara, Mexico. You will design, verify, and deliver analog, mixed-signal and full-chip layouts, guiding sub-block layouts and coordinating with global teams to meet project milestones.

The role requires strong expertise in planar and FinFET CMOS processes, Cadence VLE/VXL and Mentor Calibre DRC/LVS, and hands-on layout of critical blocks like PLLs and sensors.

Formación

• 7+ years' experience in analog/custom layout design in advanced CMOS process and technology nodes (Planar, FinFET).
• BE or MTech in Electronic/VLSI Engineering, or related field.
• Expertise in Cadence VLE/VXL and Mentor Calibre DRC/LVS is a must.
• Hands-on experience creating layout for critical blocks (e.g., Temp sensor, PLL, ADC, DAC, LDO).
• Knowledge of Analog Layout fundamentals and effects on speed, power and area.
• Ability to translate design constraints into high-quality layouts.

Responsabilidades

• Design and development of analog, mixed-signal, and digital blocks with full-chip integration.
• Perform layout verification (LVS/DRC/Antenna) and quality checks.
• Ensure on-time delivery of block layouts of acceptable quality.
• Lead planning, scheduling, and delegation across multiple projects.
• Mentor junior and senior team-members on sub-block layouts and reviews.
• Collaborate with global engineering teams to ensure layout project success.

Conocimientos

Analog layout

Custom layout

CMOS process

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Block-level layout

Layout verification concepts

Educación

BE in Electronic/VLSI Engineering

MTech in Electronic/VLSI Engineering

Herramientas

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Descripción del empleo

Micron Technology seeks a Layout Design Staff Engineer for its HBM team in Guadalajara, Mexico. You will design, verify, and deliver analog, mixed-signal and full-chip layouts, guiding sub-block layouts and coordinating with global teams to meet project milestones.

The role requires strong expertise in planar and FinFET CMOS processes, Cadence VLE/VXL and Mentor Calibre DRC/LVS, and hands-on layout of critical blocks like PLLs and sensors.