ASIC Timing and Methodology Engineer

Qualcomm; Tijuana; Presencial; MXN 300.000 - 700.000; Jornada completa

Descripción de la vacante

Qualcomm is seeking a Timing Engineer to drive timing analysis across mobile, compute, automotive and IoT platforms. You will work with block/IP-level and system-level timing, supporting 5nm, 4nm and beyond process technologies.

You will partner with physical design, CAD and design-technology teams to develop flow scripts, validate timing sign-off, and ensure STA accuracy from RTL to GDS. Strong scripting in Python/Perl/TCL and C/C++ is beneficial for automation.

Formación

• BS in Science, Engineering or related field.
• Experience with timing analysis and STA methodologies.
• Familiarity with industry EDA tools and scripting.

Responsabilidades

• Perform timing analysis for SOC blocks and system-level timing closure across 5nm/4nm processes.
• Collaborate with physical design, CAD, IP teams to develop and validate timing flows.
• Conduct Spice simulations for PVT and ensure STA correlation with spice results.
• Develop timing ECOs, sign-off packages, and support complex SoC bring-up.

Conocimientos

Python

Perl

TCL

Unix shell

C/C++

ML modeling

Educación

Bachelor's degree in Science, Engineering, or related field

Herramientas

DC

DCT

DCG

Genus

Oasis

ICC2

Fusion

Innovus

Aprisa

RedHawk

SeaHawk

Voltus

Tempus

PT-SI

Descripción del empleo

General Summary

As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets.

Responsibilities

• The candidate will work with best-in‑class methodologies, tools and technology to design innovative SOC products at the block/IP‑level and at system‑level in 5nm, 4nm and beyond (process technologies).
• You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation.
• Responsible for Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation. Timing package validation across advanced process technologies using PT/PT‑SI and Tempus.
• You will facilitate and drive STA methodology for Qualcomm using PT‑SI, Tempus and best in class timing ECO tools. Work on timing sign off specification for different projects and support timing sign off for complex SOC’s. Hands on contribution for STA timing sign off.
• A timing Engineer should be able to understand all kind of intricate timing paths (digital, analog, mixed signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa, RedHawk/SeaHawk/Voltus is a plus.
• You should have good execution knowledge.
• Your contribution should improve timing convergence process across the company, design PPA, yield and support new advanced process technologies bring-up from PDK to VLSI design production.
• You should have good programming skills Python, Perl, TCL, Unix shell, C/C++.
• ML modeling experience is a plus.

Qualifications

• Bachelor's degree in Science, Engineering, or related field.

Equal Opportunity Employer

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑[e-mail] or call Qualcomm's toll‑free number. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.