Staff Design Verification Engineer, Mixed-Signal ICs

Analog Devices; Milano; In loco; EUR 80.000 - 110.000; Tempo pieno

Descrizione del lavoro

Analog Devices, Milan-based, seeks a Staff Design Verification Engineer to verify complex mixed and digital ICs and lead sub‑system verification efforts in the Data Center and Energy group. The role entails ownership of verification plans, environments, and feature verification across multiple projects.

You will work with digital blocks, high‑speed interfaces, and DSP data‑paths, employing SystemVerilog/UVM, constrained random verification, and coverage-driven techniques while mentoring junior

Competenze

• Bachelor's or Master’s degree in Electronics Engineering.
• 8+ years of experience in digital design, with at least 3 years in digital verification.
• Expertise in Verilog, SystemVerilog, UVM, object‑oriented programming, scripting, and automation with Perl or Python.

Mansioni

• Verification of sub-systems using leading‑edge verification methodologies.
• Experience with the development of verification plans and verification environments from scratch on multiple projects.
• Verification of blocks using System Verilog and UVM.
• Should have worked on scoreboard assertions, functional coverage, and formal verification, to reach verification goals
• Take complete ownership of a complex feature verification and mentor & guide junior verification engineers.
• Define and implement improvements in verification flow and methodology.
• Gate-level simulations and debugging at the sub‑system level.

Conoscenze

Verilog

SystemVerilog

UVM

Python

Perl

Automation

Constrained random verification

Debugging

Formazione

Electronics Engineering degree

Strumenti

PMBus

SPI

OTP/MTP

I2C

Descrizione del lavoro

Analog Devices, Milan-based, seeks a Staff Design Verification Engineer to verify complex mixed and digital ICs and lead sub‑system verification efforts in the Data Center and Energy group. The role entails ownership of verification plans, environments, and feature verification across multiple projects.

You will work with digital blocks, high‑speed interfaces, and DSP data‑paths, employing SystemVerilog/UVM, constrained random verification, and coverage-driven techniques while mentoring junior