Space-Grade FPGA Design Engineer — R&D (Hybrid)

Argotec S.r.l.

San Mauro Torinese

Hybrid

EUR 45,000 - 60,000

Full time

7 days ago
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Benefits offered by this job

Hybrid work policy
Professional training and career dev.
Monthly Free-Day

Job summary

Argotec S.r.l. is seeking a motivated R&D Digital FPGA Design Engineer to join our Avionics-oriented R&D unit.

You will design HDL for On-Board Computers, Power Systems, and Telecommunication solutions destined for Earth orbit and deep-space missions. You will lead HDL design flows, validate architectures, optimize timing and power, and collaborate with cross-functional teams to deliver cutting-edge space technologies.

Qualifications

  • Master’s degree in Electronic Engineering, Computer Science, or related technical fields.
  • At least 2+ years of experience in a similar role.
  • Excellent communication skills and ability to collaborate with cross-functional teams.
  • Excellent written and oral communication in English.

Responsibilities

  • Design and develop FPGA architectures starting from system-level requirements.
  • Validate digital architecture through simulation and verification activities.
  • Perform FPGA implementation, integration, and testing activities.
  • Debugging and bug tracking for developed architecture.
  • Timing and power optimization of FPGA architectures.
  • Contribute to product development activities and project planning, working closely with cross-functional engineering teams.

Skills

Digital hardware design
C/C++
SystemVerilog
Python
VHDL/Verilog
FPGA development
Hardware-in-the-loop

Education

Master's degree in Electronic Engineering
Master's degree in Computer Science

Tools

Xilinx AMD
Radiant IDE
Microchip/Microsemi IDEs
Git
Jira
TCL scripting

Job description

Argotec S.r.l. is seeking a motivated R&D Digital FPGA Design Engineer to join our Avionics-oriented R&D unit.

You will design HDL for On-Board Computers, Power Systems, and Telecommunication solutions destined for Earth orbit and deep-space missions. You will lead HDL design flows, validate architectures, optimize timing and power, and collaborate with cross-functional teams to deliver cutting-edge space technologies.

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