R&D Digital FPGA Design Engineer

Argotec; San Mauro Torinese; Hybrid; EUR 45,000 - 60,000; Full time

Benefits offered by this job

Hybrid work policy

Flexible working hours

Monthly Free-Day

Job summary

Argotec is seeking a motivated R&D Digital FPGA Design Engineer to expand its avionics team, developing HDL for On-Board Computers, Power Systems, and Telecommunication solutions for Earth orbit and deep-space missions. You will contribute from requirements to validation, collaborating with cross-functional teams.

Requirements include a Master’s in Electronic Engineering or CS, 2+ years in a similar role, and strong English communication. Hybrid work and ongoing professional growth are offered.

Qualifications

• Master’s degree in Electronic Engineering, Computer Science, or related technical fields.
• At least 2+ years of experience in a similar role.
• Excellent communication skills and ability to collaborate with cross-functional teams.
• Excellent written and oral communication in English.
• Proactive mindset and commitment to continuous learning and professional growth.

Responsibilities

• Design and develop FPGA architectures starting from system-level requirements;
• Validate digital architecture through simulation and verification activities;
• Perform FPGA implementation, integration, and testing activities;
• Debugging and bug tracking for developed architecture;
• Timing and power optimization of FPGA architectures;
• Contribute to product development activities and project planning, working closely with cross-functional engineering teams.

Skills

C/C++

SystemVerilog

Python

VHDL/Verilog

FPGA development

Lab instrumentation

HIL debugging

TCL

UVM

Education

Master’s degree in Electronic Engineering or Computer Science

Tools

Xilinx AMD IDEs

Radiant IDE

Microsemi IDEs

Git

Jira

Job description

To support our Company’s growth, we are looking for a motivated R&D Digital FPGA Design Engineer to expand a rapidly growing team within our Research and Development Unit. Reporting directly to the Lead of the R&D Avionics team, you will work on inspirational projects, contributing to the development of new products and technologies in support of next generation’s space assets.
The focus will be on designing and developing HDL for On-Board Computers, Power Systems, and Telecommunication solutions, intended for both Earth’s orbit and deep-space missions, including the Moon and Mars.

DUTIES

As an R&D Digital FPGA Design Engineer you will contribute to the design, development and prototyping of digital architecture for space applications, supporting the evolution of innovative solutions from system requirements through implementation, validation and testing.

The activities will include (but not limited to):

• Design and develop FPGA architectures starting from system-level requirements;
• Validate digital architecture through simulation and verification activities;
• Perform FPGA implementation, integration, and testing activities;
• Debugging and bug tracking for developed architecture;
• Timing and power optimization of FPGA architectures;
• Contribute to product development activities and project planning, working closely with cross-functional engineering teams.

GENERAL REQUIREMENTS

• Master’s degree in Electronic Engineering,Computer Science, or related technical fields;
• At least 2+ years of experience in a similar role;
• Excellent communication skills and ability to collaborate with cross-functional teams;
• Excellent written and oral communication in English;
• Proactive mindset and commitment to continuous learning and professional growth.

REQUIRED EXPERIENCES & SKILLS

• Very good understanding of digital hardware design;
• Very good understanding of C, C++, SystemVerilog, Python;
• Very good understanding of VHDL or Verilog;
• Good knowledge of FPGA development methods and processes;
• Knowledge of laboratory instrumentation for prototyping and testing;
• Knowledge of debug tools for and testing with hardware in the loop;
• Strong analytical mindset and structured problem-solving approach;
• Ability to manage multiple priorities and technical challenges under tight deadlines.

ADDITIONAL ASSETS

• Experience with Universal Verification Methodology (UVM);
• Experience in embedded software development (C/C++);
• Knowledge of Xilinx AMD, Radiant and Microsemi IDEs;
• Knowledge of digital interface standards for intra-board and inter-board IO;
• Usage of versioning systems (Git, Jira);
• Knowledge of scripting languages (TCL).

WHY JOIN ARGOTEC?

• Opportunity to work with highly motivated colleagues in a very innovative environment.
• Professional training and career development opportunities.
• Flexible working time schedule and a hybrid work policy.
• Monthly “Free-Day” - every second Friday: time off to dedicate to your family and/or hobbies.
• A diversified community that organizes extra-work and fun activities.

SALARY RANGE:

45.000 - 60.000 EUR

Argotec reserves the right to assess the appropriate job level and compensation package based on objective criteria emerging throughout the selection process. These evaluations will be carried out in alignment with the candidate’s seniority, skills, and experience, as well as with the scope and responsibilities of the role. Any compensation proposal will be defined in compliance with the principles of fairness, transparency, and equal opportunity, in accordance with applicable regulations.

Our selection process is built on impartiality, transparency, and equal opportunity, ensuring that every candidate is evaluated based on skills, experience, and potential. As part of our commitment to inclusivity, we actively encourage applications from individuals belonging to protected categories (Law 68/99).

At Argotec, we’re proud to be an equal opportunity employer. We celebrate diversity and inclusion, welcoming individuals of all backgrounds. This opportunity is open to everyone, regardless, for instance, of ethnic or cultural background, color, religion, sex, gender identity, sexual orientation, or national origin.

Join us in a workplace where everyone belongs.

This announcement is aimed at both sexes, under laws 903/77 and 125/91, and to people of all ages and all nationalities, under legislative decrees 215/03 and 216/03.