Senior Physical Design Engineer – AI at the Edge MCU

NXP Semiconductors NV; Sicilia; On-site; EUR 61,000 - 84,000; Full time

Job summary

NXP Semiconductors NV is forming new teams in Catania to deliver high-performance MCU and edge-processing solutions. This role focuses on physical design and implementation of complex ICs, including timing closure, floorplanning, place-and-route, and power integrity analyses, with mentoring responsibilities across the team.

You will collaborate with architecture, RTL, DFT, and packaging teams to ensure on-time product delivery while adopting advanced design methods and tools.

Qualifications

• Bachelor’s degree with 12+ years of professional experience or Master’s degree with 10+ years of professional experience.
• Experience on advance tech nodes 16ff and below is highly desirable.
• Extensive knowledge and experience in back-end implementation tasks such as timing & power, synthesis, low power implementation, power analysis, equivalence checking and STA.
• Experience at top-level will be preferred.
• Strong proficiency with industry-standard EDA tools for physical design (Cadence Innovus, Synopsys Fusion Compiler/ICC2, Ansys RedHawk/PowerSI).
• Deep understanding of Static Timing Analysis (STA) concepts, sign-off criteria, and tools (Synopsys PrimeTime).
• Power analysis and optimization techniques (UPF/CPF, clock gating, power intent).
• Experience with physical verification tools (Synopsys IC Validator, Cadence Pegasus/PVS, Mentor Calibre).
• Proficiency in scripting languages (Tcl, Python, Perl) for automation of design flows and analysis.
• Strong communication and interpersonal skills, with the ability to mentor engineers.

Responsibilities

• Floorplanning, power grid design, place and route, low power implementation, clock tree synthesis, timing closure, power/signal integrity analysis, DRC/LVS/Antenna.
• Drive the definition and implementation of physical design methodologies, flows, and best practices to optimize performance, power, and area.
• Perform comprehensive STA and ensure timing constraints are met across corners and modes.
• Conduct power integrity and signal integrity analysis and implement mitigation solutions.
• Oversee DRC, LVS, and other physical verification steps to ensure tape-out readiness.
• Collaborate with architecture, RTL, DFT, and packaging teams for smooth integration and delivery.
• Mentor junior and senior physical design engineers, fostering learning and excellence.
• Evaluate and adopt new EDA tools and technologies to improve design efficiency and quality.

Skills

Physical design

STA (static timing analysis)

Power analysis

Mentoring

Scripting (Tcl/Python/Perl)

Problem solving

Collaboration

Education

Bachelor’s degree

Master’s degree

Tools

Cadence Innovus

Synopsys Fusion Compiler/ICC2

Ansys RedHawk/PowerSI

Synopsys PrimeTime

IC Validator

Calibre

Job description

NXP Semiconductors NV is forming new teams in Catania to deliver high-performance MCU and edge-processing solutions. This role focuses on physical design and implementation of complex ICs, including timing closure, floorplanning, place-and-route, and power integrity analyses, with mentoring responsibilities across the team.

You will collaborate with architecture, RTL, DFT, and packaging teams to ensure on-time product delivery while adopting advanced design methods and tools.