Senior Physical ASIC Design Implementation Engineer

Imec India Private Limited; Milano; In loco; EUR 90.000 - 120.000; Tempo pieno

Descrizione del lavoro

IMEC in Naples, Italy seeks an experienced Physical ASIC Design Implementation Engineer to drive the back-end flow from floorplanning to tape-out. You will work directly with customers, set up flows for advanced technology nodes, and push timing, power, and PVT closure across multiple corners.

The ideal candidate has a Master’s in Electronics, 8+ years in physical implementation, and deep Cadence Innovus expertise, with strong English communication for an international team.

Competenze

• Master’s degree in Electronics Engineering.
• 8+ years of experience in physical implementation, including 12 nm down to 2 nm.
• Experience with hierarchical, multi-block, and top-level designs.
• Strong Cadence Innovus experience.
• Experience with Tempus, Quantus, Voltus desirable.
• Experience with low-power design techniques.
• Strong knowledge of static timing analysis, timing closure, signal integrity, power integrity, and physical verification.
• Excellent communication skills and ability to work in an international environment.
• Fluency in English.
• For senior role: experience as Technical Lead coordinating team priorities.

Mansioni

• Setting up and configuring the implementation flow for the selected technology node, foundry requirements, and library set.
• Setting up and implementing low-power designs using UPF
• Performing floorplanning, macro placement, and power-grid design
• Executing timing-driven placement and placement optimization
• Performing static timing analysis and design optimization for setup timing
• Implementing Clock Tree Synthesis
• Performing scan-chain reordering and re-stitching
• Executing timing-driven routing, including signal-integrity analysis
• Performing in-place optimization to achieve timing closure across modes and corners
• Debugging and resolving setup and hold violations
• Performing sign-off parasitic extraction using Quantus and generating SPEF files
• Performing sign-off static timing analysis using Tempus
• Performing sign-off power and EM/IR analysis using Voltus
• Executing physical verification, including DRC, ERC, LVS, and antenna checks
• Performing logic equivalence checking
• Supporting final sign-off closure and tape-out
• Design partitioning for hierarchical blocks and derive timing budgets from top-level constraints with the PD team
• Interact with customers to discuss specifications and project status

Conoscenze

Static timing analysis

Power integrity

Low-power design

Timing closure

Customer interaction

Formazione

Master’s degree in Electronics Engineering

Strumenti

Cadence Innovus

Descrizione del lavoro

IMEC in Naples, Italy seeks an experienced Physical ASIC Design Implementation Engineer to drive the back-end flow from floorplanning to tape-out. You will work directly with customers, set up flows for advanced technology nodes, and push timing, power, and PVT closure across multiple corners.

The ideal candidate has a Master’s in Electronics, 8+ years in physical implementation, and deep Cadence Innovus expertise, with strong English communication for an international team.