MEMS Analog & Mixed-Signal Verification Engineer

Strategic Micro Systems of NJ, LLC.; Cornaredo, Agrate Brianza; On-site; EUR 45,000 - 75,000; Full time

Job summary

STMicroelectronics in Italy's Lombardy region seeks a Mixed Signal verification engineer with 3–5 years of experience to join the MEMS sGROUP Design team. You will define and develop verification benches, create test cases, debug and study various scenarios across analog, digital and mixed-signal environments.

The role offers exposure to cutting-edge verification methodologies and opportunities to collaborate across the ASIC verification process from specification to product industrialization.

Qualifications

• Knowledge of analog ASIC verification concepts including ADC/DAC and comparators.
• Experience with SystemVerilog RNM, Verilog-AMS and mixed-signal simulations.
• Familiarity with coverage concept, digital logic gates, and Python scripting.

Responsibilities

• Define and develop verification test benches for mixed-signal designs.
• Develop verification components and test cases for simulations.
• Debug failures and create simulation cases for various studies.
• Work with advanced verification methods at subsystem and SoC levels.

Skills

Analog circuits

SystemVerilog RNM

Verilog-AMS

Analog modeling

Mixed-signal sims

Bug analysis

Python scripting

Digital logic

Job description

STMicroelectronics in Italy's Lombardy region seeks a Mixed Signal verification engineer with 3–5 years of experience to join the MEMS sGROUP Design team. You will define and develop verification benches, create test cases, debug and study various scenarios across analog, digital and mixed-signal environments.

The role offers exposure to cutting-edge verification methodologies and opportunities to collaborate across the ASIC verification process from specification to product industrialization.