MEMS Analog Senior Designer and Architect

STMicroelectronics Italia; Cornaredo; On-site; EUR 65,000 - 95,000; Full time

Job summary

STMicroelectronics Italia in Lombardy seeks a brilliant analog FE design engineer to accelerate MEMS IC definition and implementation, collaborating with system architects and cross-functional teams to deliver high-performance inertial sensors.

You will drive transistor-level implementation, verify with simulations, and coordinate with layout engineers for IP layouts and post-layout checks, contributing to product qualification and industrialization.

Qualifications

• 5+ years of experience in analog electronics design.
• Familiarity with industrialization processes and debug/char activities.
• Strong knowledge of low power and low noise design techniques.
• Experience with Spice-based tools and mixed-signal simulation.
• Knowledge of analog blocks modeling (Verilog-A/SystemVerilog).
• System-level block implementation approach is a key skill.
• Proactivity to facilitate cross-functional team discussions.
• MEMS knowledge is a strong plus.

Responsibilities

• Accelerate definition and implementation of IC in MEMS solutions.
• Collaborate with system architect to develop blocks and sub-systems.
• Coordinate with layout engineer to drive IP layout and verify post-layout performance.
• Participate in evaluation and characterization to verify functionality and performance.

Skills

Analog design

Spice-based tools

Verilog-A/SystemVerilog

System-level design

Low noise design

Cross-functional collaboration

MEMS knowledge

Education

Master’s degree in electronic engineering

Tools

Verilog-A

Job description

YOUR ROLE

The role is aimed at accelerating the definition and the implementation of IC in MEMS solutions. The requested figure is a brilliant analog FE design engineer able to propose ideas and design solutions in the context of analog front end for inertial MEMS. The activities will focus on system-level implementation, strongly interacting with other departments. The candidate’s key role is based on cooperation with the system architect, developing blocks and sub-systems to meet the overall target performance, following transistor-level implementation and all simulation/verification activities. The candidate will also work closely with the layout engineer to drive the layout activity of the designed IPs and verify the layout impact with post‑layout simulations. He/she will participate in the evaluation and characterization of the followed products to verify the functionality and the performance of the designed blocks. Technical skills and communicative attitude are key ingredients to work in a team from the product specification to the product industrialization.

QUALIFICATIONS

• Master’s degree in electronic engineering.
• At least 5 years experience in analog electronics design and familiarity with all industrialization processes and debug/char activities.
• Good knowledge of low power and low noise design techniques.
• Good knowledge of Spice‑based tools and mixed‑signal simulation environment.
• Good knowledge of analog blocks modeling (Verilog‑A/SystemVerilog real number).
• System‑level oriented block implementation approach is considered a key skill.
• Proactivity to facilitate and drive the cross‑functional team internal discussions.
• MEMS knowledge is a strong plus.

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.