Senior Digital IC Design Engineer – SOC RTL Lead

NXP Semiconductors NV; Sicilia; On-site; EUR 51,000 - 70,000; Full time

Job summary

NXP Semiconductors NV in Italy is building new teams in Catania to create high‑impact MCUs as part of intelligent AI at the Edge. You will lead the full digital IC design flow for complex SOCs, collaborating with analog, mixed‑signal, and software teams to achieve top‑tier performance and power efficiency.

The role requires 5+ years in digital IC design, extensive Verilog/SystemVerilog experience, and strong proficiency with industry EDA tools.

Qualifications

• 5+ years of experience in digital IC design.
• Expertise in Verilog/SystemVerilog for RTL design and verification.
• Experience with industry-standard EDA tools for synthesis, STA, formal verification, and simulation.
• Strong understanding of CDC, power integrity, and low‑power design.
• Proficient in scripting (Python/Perl/Tcl) for automation.
• Excellent problem-solving and collaboration skills.

Responsibilities

• Lead the full digital IC design flow for SOCs, including specification definition, RTL coding, synthesis, STA, formal verification and power analysis.
• Collaborate with analog, mixed-signal, and software teams to define interfaces and optimize performance.
• Develop and implement innovative digital architectures and design methodologies to meet performance, power, and area targets.
• Perform comprehensive design verification using simulation tools, formal verification techniques, and hardware emulation.
• Participate in post-silicon validation and debugging to ensure product quality.
• Mentor junior engineers and contribute to design process improvements and documentation.
• Stay updated on industry trends and best practices in digital IC design.

Skills

Verilog/SystemVerilog

EDA tools

CDC & power

Scripting

Mixed-signal verification

Problem solving

Leadership/communication

Education

Master's degree in Electrical Engineering

Tools

Synopsys Design Compiler

Cadence Genus

Primetime

Synopsys Formality

VCS

QuestaSim

Job description

NXP Semiconductors NV in Italy is building new teams in Catania to create high‑impact MCUs as part of intelligent AI at the Edge. You will lead the full digital IC design flow for complex SOCs, collaborating with analog, mixed‑signal, and software teams to achieve top‑tier performance and power efficiency.

The role requires 5+ years in digital IC design, extensive Verilog/SystemVerilog experience, and strong proficiency with industry EDA tools.