Senior Digital IC Design Engineer - RTL/Verilog

Renesas Electronics Corp.; Sicilia; On-site; EUR 37,000 - 50,000; Full time

Job summary

Renesas Electronics Corp. in Sicily's Catania is seeking a Senior Digital Design Engineer to contribute to next‑generation power management solutions for AI, Cloud and Data Center applications.

The role targets candidates with proven experience in digital IC design who enjoy hands‑on engineering, ownership of their work, and a curiosity for tackling new technical challenges. You will design Verilog/SystemVerilog RTL, work with verification and analog teams, and support the full design flow.

Qualifications

• A degree in Electronic Engineering or Computer Engineering.
• Around 4+ years of experience in digital IC design.
• Practical experience with Verilog or SystemVerilog and RTL simulation and debugging.
• Strong understanding of synchronous digital design, finite state machines, clocking and reset strategies.
• Familiarity with synthesis, timing constraints and clock domain crossing concepts.
• Willingness to learn and good communication in English.

Responsibilities

• Design and implement digital blocks in Verilog/SystemVerilog, translating functional requirements into robust, synthesizable RTL.
• Contribute to microarchitecture definition, discussing implementation choices with experienced designers.
• Work closely with verification and analog engineers to develop and validate digital functionality.
• Perform simulations, debug design issues and support integration at subsystem and chip level.
• Run lint and clock domain crossing checks, and help resolve issues.
• Support synthesis, timing analysis and silicon validation as you develop broader experience across the design flow.

Skills

Digital IC design experience

English communication skills

Education

Electronic/Computer Engineering degree

Tools

Verilog

SystemVerilog

RTL simulation

Job description

Renesas Electronics Corp. in Sicily's Catania is seeking a Senior Digital Design Engineer to contribute to next‑generation power management solutions for AI, Cloud and Data Center applications.

The role targets candidates with proven experience in digital IC design who enjoy hands‑on engineering, ownership of their work, and a curiosity for tackling new technical challenges. You will design Verilog/SystemVerilog RTL, work with verification and analog teams, and support the full design flow.