Senior Digital Design Engineer — RTL/Verilog, Bonus

Renesas; Sicilia; On-site; EUR 37,000 - 50,000; Full time

Benefits offered by this job

Bonus

Job summary

Renesas in Catania is seeking a Senior Digital Design Engineer to contribute to next-generation power management solutions for AI, Cloud and Data Center applications. You will design digital blocks in Verilog/SystemVerilog and work with cross-functional teams to deliver robust RTL.

The role offers a yearly salary range of €37,000 to €50,000 with potential bonus; based in Catania, it requires good English communication and a collaborative mindset.

Qualifications

• A degree in Electronic Engineering, Computer Engineering or a related discipline.
• Practical experience with Verilog or SystemVerilog and RTL simulation and debugging.
• A solid understanding of synchronous digital design, finite state machines, clocking and reset strategies.
• Familiarity with synthesis, timing constraints and clock domain crossing concepts.
• A collaborative approach, willingness to ask questions and motivation to learn.
• Good communication skills in English.

Responsibilities

• Design and implement digital blocks in Verilog/SystemVerilog, translating functional requirements into robust, synthesizable RTL.
• Contribute to microarchitecture definition, discussing implementation choices with experienced designers.
• Work closely with verification and analog engineers to develop and validate digital functionality.
• Perform simulations, debug design issues and support integration at subsystem and chip level.
• Run lint and clock domain crossing checks, and help resolve issues.
• Support synthesis, timing analysis and silicon validation as you develop broader experience across the design flow.

Skills

Verilog/SystemVerilog

RTL simulation

Finite state machines

Clock domain crossing

English communication

Collaboration

Education

Electronic Engineering or Computer Engineering degree

Job description

Renesas in Catania is seeking a Senior Digital Design Engineer to contribute to next-generation power management solutions for AI, Cloud and Data Center applications. You will design digital blocks in Verilog/SystemVerilog and work with cross-functional teams to deliver robust RTL.

The role offers a yearly salary range of €37,000 to €50,000 with potential bonus; based in Catania, it requires good English communication and a collaborative mindset.