Senior Digital Design Engineer - Automotive RTL & IP Architect

NXP Semiconductors NV; Varese; On-site; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Equal pay commitment

Annual incentive opportunities

Equity

Competitive benefits package

Job summary

NXP Semiconductors NV in Varese, Lombardy, Italy, is seeking a Senior Digital Design Engineer to design RTL blocks and subsystems using SystemVerilog/Verilog. You will work with architects and verification teams to optimize performance, power and area while ensuring safety-compliant digital designs.

The role requires 7+ years in digital IC design, strong RTL skills, and experience with synthesis, timing constraints, and mixed-signal contexts.

Qualifications

• Master's degree in Electrical Engineering or equivalent.
• Minimum 7 years of experience in digital IC design.
• Strong RTL development and SystemVerilog/Verilog expertise.
• Knowledge of synthesis, timing constraints and digital flows.
• Familiarity with CDC, reset strategies, and low-power design concepts.
• Experience with digital verification methodologies and simulation-based verification.

Responsibilities

• Develop RTL designs for complex digital blocks and subsystems using SystemVerilog/Verilog.
• Collaborate with architects, verification engineers and cross-functional teams.
• Analyze design trade-offs for performance, power, area, safety, and testability.
• Support timing closure, synthesis, and implementation activities.
• Participate in design reviews and sign-off readiness.
• Provide technical guidance to junior engineers and foster knowledge sharing.
• Collaborate across international R&D sites and IP integration efforts.
• Follow automotive standards for functional safety and quality.

Skills

RTL design

SystemVerilog

Digital IC

Synthesis

Timing constraints

DFT fundamentals

Mixed-signal IC

EDA tools

English fluency

Mentoring

Education

Master's degree in Electrical Engineering

Tools

Synopsys

Cadence

Siemens EDA

Job description

NXP Semiconductors NV in Varese, Lombardy, Italy, is seeking a Senior Digital Design Engineer to design RTL blocks and subsystems using SystemVerilog/Verilog. You will work with architects and verification teams to optimize performance, power and area while ensuring safety-compliant digital designs.

The role requires 7+ years in digital IC design, strong RTL skills, and experience with synthesis, timing constraints, and mixed-signal contexts.