Senior Digital Backend Lead — PnR & Timing

Ams Italy S.R.L.; Lazio; In loco; EUR 90.000 - 120.000; Tempo pieno

Descrizione del lavoro

ams OSRAM in Rome, Italy is seeking a Principal HS Digital Place & Route Engineer to lead the digital backend for high-speed ICs, guiding place-and-route from synthesis to tape-out and driving PPA and sign-off.

You will mentor engineers, optimize flows, evaluate EDA tools (Cadence preferred), collaborate with foundries and vendors, and push continuous improvements across multiple projects, including advanced CMOS nodes and process technologies.

Competenze

• MSc or PhD in Electrical Engineering, Microelectronics, or related field.
• 10+ years of experience in digital physical implementation and backend design.
• Proven expertise with industry-standard physical design tools and flows (Cadence EDA flows preferred).
• Strong knowledge of floorplanning, placement, CTS, routing, STA, physical verification, power integrity, and signal integrity analysis.
• Extensive experience with timing closure and sign-off methodologies.
• Experience with high-speed interfaces such as UCIe, PCIe, DDR, SerDes, USB, MIPI, or similar protocols is highly desirable.
• Experience driving methodology development and engineering best practices across multiple projects.
• Strong communication, collaboration, mentoring, and technical leadership skills.
• Ability to work independently and influence technical decisions at organizational level.

Mansioni

• Technical expert for physical implementation of high-speed digital ICs.
• Lead place-and-route implementation from synthesis through PnR to sign-off and tape-out.
• Define, deploy, and maintain digital backend methodologies, flows, and best practices.
• Drive timing closure, power, performance, and area (PPA) strategies; ensure signal integrity and physical verification.
• Mentor and develop engineers within the digital backend community.
• Lead EDA tool evaluations, methodology improvements, and flow automation initiatives.
• Support technology enablement for advanced CMOS nodes including FinFET and FD-SOI.
• Provide technical leadership across multiple projects and business units.
• Act as interface to foundries, EDA vendors, and methodology teams.
• Drive continuous improvement of backend design efficiency and quality.

Conoscenze

Digital backend

Cadence EDA

Floorplanning

Placement

Timing closure

Sign-off

High-speed interfaces

Methodology development

Leadership

Mentoring

Independent work

Formazione

MSc/PhD in Electrical Engineering

Descrizione del lavoro

ams OSRAM in Rome, Italy is seeking a Principal HS Digital Place & Route Engineer to lead the digital backend for high-speed ICs, guiding place-and-route from synthesis to tape-out and driving PPA and sign-off.

You will mentor engineers, optimize flows, evaluate EDA tools (Cadence preferred), collaborate with foundries and vendors, and push continuous improvements across multiple projects, including advanced CMOS nodes and process technologies.