Senior Analog IC Layout Engineer – RFIC/Optical Transceivers

Huawei Technologies Italia; San Giuseppe; In loco; EUR 47.000 - 60.000; Tempo pieno

Descrizione del lavoro

Huawei Milan Research Center is seeking analog IC layout engineers to support RFIC design for optical transceivers. The role requires proficiency in analog IC layout with 3+ years of BiCMOS/CMOS experience, familiarity with Virtuoso, Calibre, and parasitic extraction, and strong teamwork in a multicultural setting.

Based in Milan, the position involves developing high‑performance IC layouts and validating top to bottom designs, with English fluency and willingness to travel outside Italy.

Competenze

• Proficient in analog IC layout with >3 years in BiCMOS/CMOS technologies.
• Experience with 28nm CMOS and FinFET processes is a plus.
• Familiar with layout editing and verification tools (Virtuoso, Calibre, Parasitic extraction).
• Mastery of analog layout design rules including device matching, noise shielding, ESD, latch-up.

Mansioni

• Physical layout and verification of high-performance Analog/RF ICs for mass-production optical transceiver modules.
• Block-level to top-level layout, routing, layout verification, ERC verification, chip finishing.

Conoscenze

Analog IC layout

BiCMOS/CMOS experience

RF layout

Layout editing

Strumenti

Virtuoso

Calibre DRC/LVS/ERC

Parasitic extraction

Descrizione del lavoro

Huawei Milan Research Center is seeking analog IC layout engineers to support RFIC design for optical transceivers. The role requires proficiency in analog IC layout with 3+ years of BiCMOS/CMOS experience, familiarity with Virtuoso, Calibre, and parasitic extraction, and strong teamwork in a multicultural setting.

Based in Milan, the position involves developing high‑performance IC layouts and validating top to bottom designs, with English fluency and willingness to travel outside Italy.