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La Chips-IT Foundation cerca Ricercatori per sviluppare PDK e modelli compact per tecnologie Wide Bandgap, nell’ambito dell’iniziativa Chips Joint Undertaking Pilot Line. Il ruolo prevede sviluppo, validazione e supporto a piattaforme EDA avanzate.
Il candidato contribuirà a creare modelli affidabili derivati da TCAD e dati sperimentali, collaborando con team europei e partner industriali. Possibile sede a Pavia o Bologna, con prospettive di crescita accademica e professionale.
Fondazione Chips-IT Pavia, Pavia, IT
The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.
The Foundation is Italy’s first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.
The Chips-IT Foundation is seeking Researchers to contribute to cutting-edge research and development activities focused on the development of Process Design Kits (PDKs) and compact models for Wide Bandgap (WBG) semiconductor technologies within the framework of the European Chips Joint Undertaking Pilot Line initiative.
The project focuses on enabling the adoption of advanced SiC and GaN technologies through the development of technology-specific compact models, Process Design Kits, and their integration into state-of-the-art Electronic Design Automation (EDA) environments. The successful candidate will contribute to bridging technology development and integrated circuit design by supporting the creation of reliable design platforms for next-generation power, RF and mixed-signal applications.
This role will involve participating in the development, validation and maintenance of compact models and PDKs derived from TCAD simulations and experimental characterization data, ensuring compatibility with leading EDA tools and supporting the progressive maturation of the Pilot Line technologies. The work can be carried out either in Pavia or in Bologna.
In conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione è compreso tra Euro 30.000,00 e 60.000,00. L’ampiezza del range è finalizzata a valutare candidature con diversi livelli di seniority; l’offerta finale sarà strettamente commisurata all’effettiva esperienza e alle competenze del candidato, e sarà integrata dai benefit aziendali previsti per il ruolo.
In accordance with applicable regulations, the gross annual salary range for this position is between €30,000 and €60,000. The breadth of this range reflects our intention to consider candidates with different levels of seniority; the final offer will be commensurate with the candidate’s actual experience and qualifications and will be complemented by the benefits package associated with the role.