Lead High-Speed SerDes & PHY Validation Architect

Xsight Labs; Trentino-Alto Adige; On-site; EUR 65,000 - 100,000; Full time

Job summary

Xsight Labs is seeking a Senior SerDes & High-Speed PHY Validation Engineer to lead validation for 112G PAM4 and future 224G technologies. You will own test plans, perform advanced measurements, and collaborate across silicon, package, board, and system teams to drive product readiness.

The role emphasizes lab ownership, automation, and data-driven investigations, with opportunities to influence next-generation Ethernet PHY designs.

Qualifications

• Deep experience in SerDes and PHY validation in high-speed systems.
• Hands-on experience with PAM4-based communication systems.
• Strong understanding of BER, jitter, and equalization techniques.

Responsibilities

• Lead end-to-end validation of SerDes and PHY solutions across silicon, package, board, and system environments.
• Define validation strategies for 112G PAM4 and 224G technologies.
• Develop characterization methodologies for performance, robustness, and margins.
• Support silicon bring-up and root-cause analysis of complex issues.
• Perform advanced high-speed measurements (eye diagrams, bathtub curves, RJ/DJ/TJ).
• Document results and present findings to stakeholders.

Skills

SerDes validation

Signal integrity

PAM4 signaling

BER/margin analysis

Jitter analysis

Automation with Python

Linux environment

Education

B.Sc. or M.Sc. in Electrical Engineering

Tools

Keysight validation platforms

Oscilloscopes

BERTs

VNAs

Job description

Xsight Labs is seeking a Senior SerDes & High-Speed PHY Validation Engineer to lead validation for 112G PAM4 and future 224G technologies. You will own test plans, perform advanced measurements, and collaborate across silicon, package, board, and system teams to drive product readiness.

The role emphasizes lab ownership, automation, and data-driven investigations, with opportunities to influence next-generation Ethernet PHY designs.