High-Speed SerDes & PHY Validation Engineer

Xsight Labs; Trentino-Alto Adige; On-site; EUR 60,000 - 90,000; Full time

Job summary

Xsight Labs is seeking a motivated SerDes & High-Speed PHY Validation Engineer to join our connectivity validation team and contribute to next-generation Ethernet networking solutions for AI and data center applications.

You will validate 112G PAM4 and future 224G PHY architectures, perform eye-diagram, BER, and jitter analyses, and collaborate with SI/PI, design and system teams to deliver robust lab-tested products.

Qualifications

• 2+ years in SerDes or PHY validation or high-speed design.
• Experience with PAM4 signaling and BER measurements.
• Strong analytical and debugging skills; collaborative.
• Familiar with lab equipment like oscilloscopes, BERTs, VNAs.

Responsibilities

• Validate and characterize high-speed Ethernet SerDes and PHY across silicon, package, board, and system.
• Perform eye-diagram, jitter, and margin analyses under varying conditions.
• Support silicon bring-up and debug; assist root-cause investigations.
• Develop validation automation and data analysis workflows.
• Document tests and present findings to teams.

Skills

SerDes validation

Signal integrity

BER measurements

Jitter analysis

Equalization concepts

Education

B.Sc. or M.Sc. in Electrical Engineering

Tools

Oscilloscopes

BERTs

VNAs

Job description

Xsight Labs is seeking a motivated SerDes & High-Speed PHY Validation Engineer to join our connectivity validation team and contribute to next-generation Ethernet networking solutions for AI and data center applications.

You will validate 112G PAM4 and future 224G PHY architectures, perform eye-diagram, BER, and jitter analyses, and collaborate with SI/PI, design and system teams to deliver robust lab-tested products.