Principal Digital Design Engineer (f/m/div)

Infineon Technologies; Cascina Priora; In loco; EUR 57.600 - 79.200; Tempo pieno

Descrizione del lavoro

Infineon Technologies in Italy is seeking a Principal Digital Design Engineer to lead the RTL/Verilog design of advanced Analogue/Mixed‑Signal IPs and drive silicon bring‑up.

You will own the full digital design flow RTL‑to‑GDS, coordinate with System and Analogue teams, and mentor engineering staff to achieve robust timing closure and design excellence.

The role requires 10+ years of RTL experience and fluent English, with a strong leadership mindset and hands‑on expertise in high‑speed SerDes.

Competenze

• 10+ years of RTL design experience for Analogue/Mixed‑Signal IPs.
• Leadership experience guiding engineering teams.
• Expert in Verilog/SystemVerilog.

Mansioni

• Lead the Digital Design team from specification to silicon bring‑up.
• Design digital components for analog/mixed‑signal IPs including high‑speed SerDes, PHYs, PLLs.
• Own digital signoff across RTL‑to‑GDS, LEC, linting, CDC/RDC, ATPG.

Conoscenze

Leadership

Verilog/SystemVerilog

RTL design

Digital design flow

English fluent

Formazione

Bachelor's degree in Electrical Engineering or related field

Advanced degree (MS/PhD) preferred

Descrizione del lavoro

As a Principal Digital Design Engineer in our Research & Development team, you’ll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Responsibilities

• Lead the Digital Design team from specification definition to successful silicon bring‑up.
• Design digital components for advanced Analogue/Mixed‑Signal IPs, including high‑speed SerDes, PHYs, and PLLs.
• Own digital signoff activities across the full flow (RTL‑to‑GDS, LEC, linting, CDC/RDC, ATPG).
• Collaborate closely with System Architecture teams to define and implement complex digital functions (e.g., adaptive channel equalization).
• Partner with Analogue Design teams to ensure seamless digital control and integration of analogue blocks.
• Work alongside Digital Physical Design teams to achieve robust timing closure and clean signoff.
• Engage with internal customers and Verification teams to drive high‑quality IP definition, integration, and design excellence.

Qualifications

• 10+ years of experience in RTL design for Analogue/Mixed‑Signal IPs.
• Strong leadership mindset with the ability to guide and inspire engineering teams.
• Expert‑level proficiency in Verilog/SystemVerilog.
• Solid understanding of the full digital design flow (RTL‑to‑GDS, LEC, linting, CDC/RDC, ATPG).
• Good knowledge of Digital Test Methodologies.
• Experience in high‑speed SerDes is highly valued.
• Fluency in English (mandatory).

Benefits

Bachelor's or advanced degree in Electrical Engineering or related field; experience in digital design for advanced IPs; salary range 57,600€–79,200€ (annual base pay plus target variable compensation). Employees also benefit from a comprehensive total rewards package, which may include additional compensation and benefits depending on local regulations and company policies.

Infineon is committed to diversity, inclusion, and equal opportunity. We welcome applicants of all backgrounds and encourage you to apply even if you do not fully meet all requirements.