Junior RISC-V Digital Design Engineer & SoC Innovator

Fondazione Chips-IT

Cascina Priora

On-site

Full time

14 days+

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Benefits offered by this job

Competitive compensation
Lunch tickets
Private health care coverage
Structured growth path
Networking opportunities
Tax deductions for candidates from abroad

Job summary

A nonprofit research organization in Italy seeks junior researchers to engage in innovative projects on digital design and RISC-V architectures. Responsibilities include supporting R&D efforts, assisting with design and verification of digital systems, and collaborating with experienced team members. The ideal candidate should have a Master's degree (or near completion) in Electrical or Computer Engineering, coupled with knowledge of hardware description languages and a strong desire to learn in a cutting-edge environment. Competitive compensation and benefits are offered.

Qualifications

  • Master's degree (or near completion) in Electrical/Computer Engineering focused on digital design.
  • Fundamental knowledge of HDL and digital design tools required.
  • Eagerness to learn and grow in digital design and processor architecture.

Responsibilities

  • Support research and development of digital designs based on RISC-V architecture.
  • Assist in design and verification of digital building blocks.
  • Collaborate with senior team in technical discussions and design reviews.

Skills

Hardware description languages (HDL)
Analytical skills
Problem-solving skills
Team collaboration

Education

Master's degree in Electrical Engineering or Computer Engineering

Tools

Verilog
VHDL

Job description

A nonprofit research organization in Italy seeks junior researchers to engage in innovative projects on digital design and RISC-V architectures. Responsibilities include supporting R&D efforts, assisting with design and verification of digital systems, and collaborating with experienced team members. The ideal candidate should have a Master's degree (or near completion) in Electrical or Computer Engineering, coupled with knowledge of hardware description languages and a strong desire to learn in a cutting-edge environment. Competitive compensation and benefits are offered.
Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Junior Digital Design and RISC-V Architectures Engineer
Junior Digital Design and RISC-V Architectures Engineer

Fondazione Chips-IT • Cascina Priora

On-site
Confidential
Competitive compensation
Lunch tickets
Private health care coverage
+3
Senior Analog and Mixed Signal Integrated Circuit Design Research Engineer
Senior Analog and Mixed Signal Integrated Circuit Design Research Engineer

Fondazione Chips-IT • Cascina Priora

On-site
EUR 70,000 - 90,000
Lunch tickets
Private health care
Structured growth path
+3
Head of Silicon Design & Validation Infrastructure
Head of Silicon Design & Validation Infrastructure

Fondazione Chips-IT • Bologna

On-site
EUR 90,000 - 140,000
Senior RISC-V Standards Engineer – CPU Architecture
Senior RISC-V Standards Engineer – CPU Architecture

Qualcomm • Milano

On-site
EUR 120,000 - 150,000
Lead of Silicon Design Support Infrastructure
Lead of Silicon Design Support Infrastructure

Fondazione Chips-IT • Bologna

On-site
EUR 90,000 - 140,000
Lunch tickets
Private health care coverage
Hybrid work policy
+1
Firmware Engineer - RISC-V Crypto (Hybrid)
Firmware Engineer - RISC-V Crypto (Hybrid)

ADENTIS Italia • Roma

Hybrid
EUR 30,000 - 40,000
Contratto a Tempo Indeterminato
Formazione continua
Piano di crescita professionale
Hybrid Junior R&D Engineer: Software, Electronics & AI
Hybrid Junior R&D Engineer: Software, Electronics & AI

ENLABOR • Delebio

Hybrid
EUR 35,000 - 45,000
Research Engineer – RF Integrated Circuit Design
Research Engineer – RF Integrated Circuit Design

Fondazione Chips-IT • Lombardia

Hybrid
EUR 25,000 - 55,000
Lunch tickets
Private health care
Structured growth path
+4
Senior Digital IC Design Engineer (RTL/Verilog)
Senior Digital IC Design Engineer (RTL/Verilog)

NXP Semiconductors • Catania

On-site
EUR 51,000 - 70,000
Annual incentive opportunities
Equity participation
Comprehensive benefits package
+1
EDA Design Center Lead for SoC Innovation
EDA Design Center Lead for SoC Innovation

Fondazione Chips-IT • Cascina Priora

On-site
Confidential