Junior Design Verification Engineer – Wireless ASICs for LEO

Amazon Inc.; Asti; Ibrido; EUR 101.000 - 141.000; Tempo pieno

Vantaggi offerti da questo lavoro

Health insurance

401(k) matching

Paid time off

Parental leave

Descrizione del lavoro

Amazon Leo is seeking a Junior Design Verification Engineer to define and implement digital SOC verification for LEO satellites, contributing to high-speed wireless modem design and test environments. You will work with RTL, Matlab models, and UVM-based testbenches to drive coverage and ensure robust verification across CMOS generations.

The role emphasizes automated regression environments, collaboration with design and systems teams, and participation in system-level verification.

Competenze

• Bachelor's degree or equivalent experience in Electrical/Communications Engineering or CS
• 2+ years in verification, preferably in communication systems
• 2+ years in UVM

Mansioni

• Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
• Participate in the validation of ASIC implementations in Verilog/SystemVerilog
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM
• Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database

Conoscenze

Verification experience

Modem DV

SystemC

Matlab familiarity

C language

Formazione

Bachelor's degree in Electrical / Communications Engineering or Computer Science, or related field

Strumenti

UVM

Verilog/SystemVerilog

Matlab models

Descrizione del lavoro

Amazon Leo is seeking a Junior Design Verification Engineer to define and implement digital SOC verification for LEO satellites, contributing to high-speed wireless modem design and test environments. You will work with RTL, Matlab models, and UVM-based testbenches to drive coverage and ensure robust verification across CMOS generations.

The role emphasizes automated regression environments, collaboration with design and systems teams, and participation in system-level verification.