Computational EM Engineer for High‑Speed Interconnects

Huawei Technologies Italia; Italia; In loco; EUR 60.000 - 75.000; Tempo pieno

Descrizione del lavoro

Huawei Technologies Italia, via CHEI at the Milan Research Center, develops advanced computational methods for next‑generation ICT systems. The Computational EM Engineer role focuses on methods, EM models, and engineering software for high‑speed interconnect analysis and optimization.

You will collaborate with hardware and signal integrity engineers to translate simulations into practical design guidelines, building reusable workflows across PCB, package, and interconnect challenges.

Competenze

• Advanced degree and/or 5+ years of relevant experience.
• Strong background in computational electromagnetics.
• Experience with electromagnetic simulation tools.
• Ability to develop reusable software tools.

Mansioni

• Develop EM methodologies for modeling and optimization of high‑speed interconnects.
• Design numerical algorithms and reusable software to improve productivity and scalability.
• Build physics-based and reduced-order models and automation pipelines.
• Validate simulations and distinguish physical effects from numerical artifacts.
• Apply computational methods to PCBs, packages, connectors, cables, and complete channels.
• Collaborate with hardware and signal integrity engineers to translate results into design guidelines.
• Contribute to long‑term technical roadmap with novel methodologies.

Conoscenze

Analytical thinking

English communication

Problem solving

Team collaboration

Strong mathematical foundations

Formazione

Advanced degree in EE/Physics/Applied Mathematics/ Computational Science

Strumenti

HFSS

CST

COMSOL

ADS

Python

C++

MATLAB

Descrizione del lavoro

Huawei Technologies Italia, via CHEI at the Milan Research Center, develops advanced computational methods for next‑generation ICT systems. The Computational EM Engineer role focuses on methods, EM models, and engineering software for high‑speed interconnect analysis and optimization.

You will collaborate with hardware and signal integrity engineers to translate simulations into practical design guidelines, building reusable workflows across PCB, package, and interconnect challenges.