Vlsi Trainer

Maven Silicon; Hyderabad; On-site; INR 600,000 - 900,000; Full time

Job summary

Maven Silicon in Hyderabad, India seeks a seasoned trainer with 3-10 years in VLSI to deliver hands-on training on Digital design, SV/UVM/Verilog, VHDL and DFT tools, and to support back-end design projects.

The role involves debugging source code in Verilog, SV and UVM, plus training delivery and ongoing support for learners. Strong communication and presentation skills are essential to guide students through complex concepts and practical exercises.

Qualifications

• Extensive hands on and teaching experience on Digital / SV/UVM/Verilog / VHDL /DFT tools.
• Extensive experience in Back-end design.
• Experience on Mentor Graphics EDA flow is an added advantage.
• Responsible for development and support of Projects.
• Responsible for Debugging the source codes in Verilog, SV, and UVM.
• Responsible for Training Delivery and Support.

Responsibilities

• Extensive hands on and teaching experience on Digital / SV/UVM/Verilog / VHDL /DFT tools.
• Extensive experience in Back-end design.
• Experience on Mentor Graphics EDA flow is an added advantage.
• Responsible for development and support of Projects.
• Responsible for Debugging the source codes in Verilog, SV, and UVM.
• Responsible for Training Delivery and Support.

Skills

Digital

Verilog

VHDL

SystemVerilog

UVM

DFT

Back-end design

Training

Education

B.E./B.Tech./M.Tech in VLSI/ECE/EEE

Tools

Mentor Graphics EDA flow

Job description

Experience : 3-10 Years

Education : B.E. or B.Tech or MTech VLSI / ECE/EEE

Industry Type : Education / E-Learning / Semiconductor

Functional Area : Training

category: Technical

Filter: Full- time

Job Description

• Extensive hands on and teaching experience on Digital / SV/UVM/Verilog / VHDL /DFT tools
• Extensive experience in Back-end design
• Experience on Mentor Graphics EDA flow is an added advantage
• Responsible for development and support of Projects.
• Responsible for Debugging the source codes in Verilog, SV, and UVM.
• Responsible for Training Delivery and Support

Desired Candidate Profile

• Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back end design
• 3 to 8 years industry/teaching experience
• Good communication & presentation skill