RTL/FPGA Design Engineer(Experienced)

AumRaj Design Systems Pvt Ltd.; Ahmedabad District; On-site; INR 1,800,000 - 2,600,000; Full time

Job summary

AumRaj Design Systems Pvt Ltd. seeks an experienced RTL/FPGA Design Engineer to contribute to the full FPGA development lifecycle in Ahmedabad and Bangalore.

You will work on Verilog/SystemVerilog or VHDL RTL, implement IP blocks, verify designs, optimize timing, and collaborate with global teams to deliver high-performance FPGA solutions. Applicants should have 3–7 years of experience, BE/B.Tech or ME/M.Tech in Electronics/VLSI Design, and hands-on with Quartus, Vivado, ModelSim, ISE, and

Qualifications

• BE/B.Tech in Electronics/ECE with good academics.
• ME/M.Tech in Electronics/VLSI Design with good academics.
• Experience with Verilog/SystemVerilog or VHDL for design and verification.
• Deep understanding of FPGA design flow, IP integration, and design collateral.
• Ability to develop small IP blocks from scratch and perform basic functional verification.
• Familiarity with SPI, I2C, UART and AXI protocols.
• Knowledge of IP/system design specifications and standards.
• Experience with Quartus II, QuestaSim/ModelSim, ISE, Vivado, and Libero.

Responsibilities

• RTL programming using Verilog/SystemVerilog or VHDL.
• Manage and execute FPGA design development flow.
• Hands-on with FPGA development tools (Quartus, ModelSim, Vivado, ISE, Libero).
• Perform functional verification and timing optimization.
• RTL code optimization to meet timings and resource usage.
• Support FPGA-based product development across phases.
• Contribute to system architecture design.
• Test and troubleshoot hardware implementations.

Skills

RTL programming

FPGA design flow

Verilog/SystemVerilog

IP integration

Verification

AXI protocol

SPI/I2C/UART

DDR/QSPI

Code optimization

Team collaboration

Education

BE/B.Tech in Electronics/ECE

ME/M.Tech in Electronics/VLSI Design

Tools

Quartus II

QuestaSim

ModelSim

ISE

Vivado

Libero

Job description

VLSI Domain

RTL/FPGA Design Engineer (Experienced)

Min 3 - 7 Years of Experience

BE/B.Tech in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or closely related degree

Ahmedabad, Bangalore

Roles & Responsibilities

• RTL programming (Verilog/System Verilog or VHDL).
• Knowledge of complete FPGA Design Development flow.
• Hands-on with FPGA Development Tools (Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc.).
• Functional verification using Verilog/System Verilog or VHDL.
• RTL Code Optimization to meet timings and fit on-chip resources.
• Support all phases of FPGA based product development activities.
• System Architecture Design.
• Testing and troubleshooting of hardware.

Skills Requirements

• BE/B.Tech in Electronics/Electronics & Communication from a recognized university with a good academic record.
• ME/M.Tech in Electronics/VLSI Design from a recognized university with a good academic record.
• Experience with Verilog/SystemVerilog or VHDL for design and verification.
• In-depth understanding of FPGA design flow/methodology, IP integration, and design collateral.
• Should be able to develop the small blocks of IP from scratch and do basic functional verification.
• Should be familiar with protocols like SPI, I2C, UART and AXI.
• Understanding of standard/specification/application for IP design or system design.
• Knowledge of Altera Quartus II Tool, Questasim, Modelsim.
• Knowledge of Xilinx tools like ISE, and Vivado.
• Knowledge of Microsemi tools like libero.
• Knowledge of USB, Ethernet, and external memories such as DDR, QDR RAM and QSPI-NOR based Flash.

Personal Competency

• Self-motivated to learn and contribute.
• Ability to work effectively with global teams.
• Able and willing to work in a team-oriented, collaborative environment.
• A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment.
• Proven analytical and creative problem-solving abilities.
• Passionate about writing clean and neat code that adheres to coding guidelines.