VLSI ASIC SOC System Verilog Architect

HCL Technologies Limited; Hyderabad, Chennai, Bengaluru; Hybrid; INR 4,000,000 - 7,000,000; Full time

Job summary

HCL Technologies Limited is seeking an experienced SoC Architect to own the system-level architecture of complex SoCs, guiding from specification to final tapeout. You will lead architecture decisions, define interconnect and memory hierarchies, and drive power, performance, and cost targets across Design, Verification, Physical Design and Firmware teams.

The role requires 10+ years in ASIC/SoC development with architecture ownership, and advanced degrees.

Qualifications

• MS/PhD in Electrical or Computer Engineering or equivalent experience.
• 10+ years of ASIC/SoC development with architecture ownership.
• Track record leading full-chip or major subsystem architecture.

Responsibilities

• Own the SoC system-level architecture, memory hierarchy, and interconnect topology.
• Balance performance, power, area, cost, and schedule tradeoffs with cross-functional teams.
• Lead architecture reviews, sign-off milestones, and technical decisions across multiple groups.
• Define IP sourcing strategy, reuse methodologies, and integration interfaces.
• Act as the primary escalation point for architecture and implementation challenges.

Skills

SoC Architecture

NoC / Interconnect Design

Memory & Cache Hierarchies

Low-Power Design

DVFS

Physical Design Constraints

PPA Optimization

IP Integration & Reuse Strategies

System-Level Performance Modeling

Technical Leadership

Education

MS/Ph.D. in Electrical Engineering or Computer Engineering

Job description

Are you passionate about defining the architecture of next-generation semiconductor products?

Join our team as a SoC Architect and drive the end-to-end architectural vision for complex SoCs, from specification and partitioning to implementation, tapeout, and silicon success.

Role Overview

As a SoC Architect, you will own the system-level architecture of the chip, defining subsystem boundaries, memory hierarchy, interconnect topology, power strategy, and performance targets. You will be the technical leader responsible for balancing performance, power, area, cost, and schedule tradeoffs while working closely with cross-functional engineering teams.

Key Responsibilities

Define and own SoC architecture, subsystem partitioning, memory hierarchy, NoC/bus architecture, and power/clock domains.

Drive architectural tradeoff decisions across performance, power, area (PPA), cost, and schedule.

Lead architecture reviews, sign-off milestones, and technical decision-making across Design, Verification, DFT, Physical Design, Firmware, and Product teams.

Own area, power, timing, and cost budgeting across all SoC subsystems.

Define IP sourcing strategy, reuse methodology, integration architecture, and interface specifications.

Act as the primary technical escalation point for architecture and implementation challenges.

Collaborate with stakeholders to translate product requirements into scalable silicon solutions.

Required Qualifications

M.S./Ph.D. in Electrical Engineering, Computer Engineering, or equivalent experience.

10+ years of experience in ASIC/SoC development with significant architecture ownership.

Proven track record of leading full-chip architecture or major subsystem architecture for successful silicon products.

Strong expertise in:

• SoC Architecture
• NoC / Interconnect Design
• Memory & Cache Hierarchies
• Low-Power Design & DVFS
• Physical Design Constraints
• PPA Optimization
• IP Integration & Reuse Strategies
• System-Level Performance Modeling

Preferred Experience

Advanced process nodes and multi-generation SoC development.

Mobile, Automotive, Data Center, Networking, AI/ML, or Edge Computing products.

Hardware-Software Co-design and Firmware Architecture.

Performance, Power, and Architectural Modeling Frameworks.

Location

Bangalore/Chennai/Hyderabad/Kochi

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