Silicon Principal Architect

Ample Success HR; Bengaluru; On-site; INR 5,000,000 - 9,000,000; Full time

Job summary

Ample Success HR in Bengaluru seeks a Principal Semiconductor Architect to bridge software requirements and hardware, translating targets into high-performance micro-architectural specs for the full chip lifecycle from concept to tape-out. You will define SoC architecture, translate requirements, and model performance and power across teams. 15+ years’ experience, tape-out leadership, DDR/HBM/NoC and PCIe/CXL expertise required. Proficiency in SystemVerilog, C/C++, or Python for modeling.

Qualifications

• 15+ years in hardware architecture and micro-architecture.
• Proven history of leading tape-outs of complex production silicon.
• Deep knowledge of memory hierarchies (DDR/HBM) and NoC.
• Experience with DDR/HBM and high-speed protocols (PCIe, CXL).
• Proficient in SystemVerilog, C/C++, or Python for modeling.
• Experience with architectural simulation tools.

Responsibilities

• Define SoC architecture for complex systems-on-chip, including cores and interconnects.
• Translate software, product and market requirements into hardware specs.
• Build and use system-level performance and power models.
• Collaborate with software, RTL, verification, and physical implementation teams.
• Evaluate technology, IP, and packaging options; guide validation.

Skills

Leadership in hardware architecture

Tape-out leadership

System-level modeling

Education

Bachelors/Masters/PhD in EE/EC/CS

Tools

SystemVerilog

C/C++

Python

Architectural simulation tools

Job description

A Principal Semiconductor Architect to who can bridge the gap between software requirements and physical hardware. You will translate system targets into high-performance, energy-efficient micro-architectural specifications, balancing power, performance, area, and cost (PPAC) to drive the entire chip lifecycle from concept to tape-out.

Core Responsibilities

• Define SoC Architecture: Lead the architectural definition of complex Systems-on-Chip (SoCs), including compute cores, memory subsystems, and high-speed interconnects.
• Translate Requirements: Convert high-level software, product, and market requirements into detailed, actionable hardware specifications.
• Model & Simulate: Build and utilize system-level performance and power models to validate architectural choices and optimize workloads.
• Drive Co-Design: Collaborate with software, hardware design (RTL), verification, and physical implementation teams to ensure structural viability.
• Evaluate Technology: Assess and integrate third-party IP, advanced packaging technologies (2.5D/3D), and emerging interface standards.
• Guide Validation: Support post-silicon validation, debugging, and performance tuning to bring the silicon to production.

Key Requirements & Qualifications

• Education: Bachelor’s / Master’s / PhD in Electrical Engineering, Electronics Engineering or Computer Science.
• Experience: 15+ years of hardware architecture, micro-architecture, digital logic design experience.
• Track Record: Proven history of leading architecture for successful tape-outs of complex production silicon
• Technical Depth: Deep knowledge of memory hierarchies (DDR/HBM), on-chip networks (NoC), and high-speed protocols (PCIe, CXL).
• Tools & Languages: Proficiency in SystemVerilog, C/C++ or Python (for modeling), and architectural simulation tools

Interested in this role?